Abstract: A data processing apparatus in which a memory (10) is accessed at addresses stored in an address regiser (20). An incrementation circuit (38) successively increments or decrements the address stored in the principal register, under the control of an address cycling circuit (22). A pair of auxiliary registers (30, 35) respectively store the minimum and maximum address values to be reached in the principal register, and a comparison circuit (37) determines when the address therein matches the minimum or maximum value. The address cycling circuit, together with the comparison circuit, loads the principal register with the minimum address value when the address therein reaches the maximum value, the address therein thereafter being decremented, and loads it with the maximum address value when the address therein reaches the minimum value, the address therein thereafter being incremented.