Abstract: A video signal processor operates an arithmetic logic unit to perform on-the-fly compression of image data as the image data is input to the processor. The on-the-fly compression provides a data input pipeline that stores compressed image data for a large image area in a relatively small buffer in the processor. A hierarchical motion estimation process can first search the large image area by comparing blocks of the compressed image data to a compressed reference block. The hierarchical search process can then store uncompressed image data for a smaller image area and search the smaller image area to accurately determine a motion vector for the reference block.

Abstract: A quantization circuit includes a set of prime number dividers that can be implemented as look-up tables and a shifter. A shifter implements divisions by prime number (two) and by powers of two. Multiplexing circuitry interconnects the prime number dividers to permit performance of a series of prime number divisions in a single clock cycle. The quantization circuit can thus implement one-cycle divisions by divisors that are products of the prime numbers and powers of two in the series that the multiplexing circuitry selects. For divisors that are longer series of the prime numbers implemented in the quantization circuit, the quantization circuit can implement multi-cycle divisions by feeding an output signal back through further series of the prime number dividers.

Abstract: A video processor has motion estimation, pixel processing, and general processing modes. In the processor, an internal memory acts as a buffer containing a search window in motion estimation mode and as a scratch pad in pixel and general processing modes. Another internal memory acts as a buffer for a reference block in search mode and as a register file in pixel and general processing modes. Both internal memories provide parallel pixel-size data elements in pixel processing mode and larger data elements in general processing mode. An ALU in the processor has multiple slices that operate independently for parallel processing in motion estimation and pixel processing modes and cooperatively to provide a larger data width for general purpose processing mode.