Abstract: A variable frequency waveform synthesizer includes a programmable counter coupled to count cycles of a single reference clock signal and recycle at an intermediate frequency determined by a count number selected in response to frequency selection signals. Because of the need to select an integral count number, a count number that is exactly required for a desired frequency must be rounded off to the nearest integral number and the higher the number the lower the percent round off error. Thus, the percentage frequency error for a plurality of different waveforms that are synthesized as a sequence of discrete steps derived from a common reference clock signal is reduced by dividing the reference frequency to obtain an intermediate frequency signal and dividing each period of the intermediate frequency signal into a plurality of not necessarily equal steps to obtain a stepping signal commanding step changes in the synthesized waveform.