Abstract: A gateway data port for coherently transferring multiple-bit input data words in series as part of an input data chain onto an input data line that serially connects the gateway data port and other data ports to a receiver and for coherently transferring multiple-bit output data words from an output data line that serially connects the gateway data port and other data ports to a transmitter. The input data words are provided to the gateway data port asynchronously with the transfer onto the input data line; and the output data words are transmitted over the output data line as part of an output data chain to the gateway data port asynchronously with the transfer from the output data line. The input data words are transferred coherently through an asynchronous receiver and a buffer into an input data shift register, which includes a serial block of adjacent input data register stages defining a plurality of data word bit positions in the input data chain.

Abstract: An improved telemetry system for transferring data signals to and from a plurality of serially-connected, addressable data ports. The telemetry system includes a plurality of serially-connected input/output (I/O) data ports; an output data line and an input data line serially-connecting the data ports; a clock signal generator for generating clock pulses and frame pulses for common system timing; and a clock line for carrying the clock pulses and frame pulses from the clock signal generator to the ports. Each data port contains an address circuit which determines when during each frame that port is enabled to transfer data an input shift register for loading data signals for transfer onto the input data line at a time indicated by a transfer signal provided by the address circuit; and an output shift register for temporarily storing output data signals received from the output data line immediately prior to the provision of the transfer signal by the address circuit.

Abstract: A data transfer system having a serially distributed chain of input data ports and a serially distributed chain of output data ports is monitored to count the number of ports in each chain and to determine whether there has been a change in the configuration of the system by comparing the presently obtained counts with counts stored from previous monitoring. To monitor the system, successive data frames are serially shifted bit-by-bit from a transmitter over an output data line connecting the output data ports. Each frame contains a single unique bit in a data bit position that changes progressively from one frame to the next in relation to the position of the data ports. Upon the conclusion of each frame shift, a return data transfer circuit transfers data from the output data line to the input data line.

Abstract: A telemetry system for transferring blocks of pulsed data signals to and from daisy chains of addressable data ports. The telemetry system includes a daisy chain of input data ports and a parallel daisy chain of output data ports; an output data line and an input data line each serially-connecting the data ports; a clock signal generator for generating square wave clock pulses for common system timing; and a clock line for carrying the clock pulses to the ports. Each data port contains an address circuit which determines when during each block of serially-transmitted data signals that port is enabled to transfer data independent of its physical location on the data line. Data signals are transmitted over the data lines during high-state intervals of the clock signal and control signals such as frame signals, are transmitted over the data lines during the low-state intervals of the clock signals.

Abstract: A telemetry system for a plurality of distributed equipment controls and/or equipment monitors that does not require complex masses of wires. The telemetry system includes an output channel for communicating control signals to the equipment controls and/or an input channel for communicating monitored signals from the equipment monitors. The output channel includes a first block of transmitter register stages for receiving a set of control signals from a controller; and a second block of distributed, series-connected parallel-output control register stages connected in series with the first block for receiving the control signals in series from the first block, and respectively positioned at the equipment controls for connection to the equipment controls for providing the control signals to the equipment controls.

Abstract: A buffer system for interfacing an intermittently accessing data processor to a communications system in which the transfer of data bits is clocked at a predetermined rate in response to clock pulses provided by a communications system clock signal. The system includes a random access memory (RAM) for storing input signal data bytes received from an input communications channel of the communications system and for storing output signal data bytes for transmission to an output communications channel of the communications system; and a port interface section that is responsive to the system clock signal for serially receiving and transmitting input signal data bytes from the input channel, for storing output signal data bytes to the output channel and for providing a flag signal to demarcate the data bytes.