Abstract: A device for debugging an electronic circuit manufactured from an initial program in hardware description language, HDL, comprising an instrumentation unit capable of receiving the initial program; receiving an additional program describing determined functions; determining an additional circuit to be incorporated into the electronic circuit from the additional program, capable of setting to a determined value a signal selected from among an input signal, an output signal, or a signal internal to the additional circuit; and providing a modified program in HDL language incorporating a description in HDL language of the additional circuit; and a debugging unit capable of debugging a modified electronic circuit manufactured from the modified program, the debugging unit being capable of communicating with the additional circuit to control the setting to the determined value of the selected signal.

Abstract: A device for debugging an electronic circuit manufactured based on an initial program in hardware description language comprising an instrumentation unit capable of determining a first additional circuit capable of activating a first observation signal representative of the operation of a portion of the electronic circuit corresponding to a determined portion of the initial program, a second additional circuit capable of receiving at least one input signal and of activating a condition signal when a condition on the input signal is fulfilled, a third additional circuit capable of activating a second observation signal when the condition signal is activated, a fourth additional circuit capable of memorizing data representative of the order of activation of the first and second observation signals and capable of providing a modified program incorporating the additional circuits, and a debugging unit capable of debugging a modified electronic circuit manufactured based on the modified program.

Abstract: A testable electronic system includes testable elements having standardized test interfaces for organizing the elements in chains which behave like shift registers to ensure the exchange of test information. Each element are either a component including an identifier characterizing the behavior of the test of the component and accessible by the test interface of the component, or a switch for organizing a chain in sub-chains which can be individually selected through channels of the switch. The system includes master switches which define respective sub-sets of elements, a specific channel of each master switch being reserved to access an identifier characterizing the test organization of the associated sub-set.