Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing engine and a memory system such that write data is buffered and information based upon reads and writes is recorded. Memory read data is returned speculatively since the packet processing engine is processing packets in parallel and not necessarily in sequence. Information is maintained allowing the detection of a speculative read that was incorrect (i.e. a memory conflict). When a memory conflict is detected, a restart signal is generated and the information for the associated packet identifier or sequence number is flushed.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the packet processing engine and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. Both a strict and alternate packet ordering are evaluated, such that the semantic ordering of packets is delayed until necessary to ensure that a consistent order exists. Such a late order binding mechanism is used to allow packets to be defined in any order so long as they obey a consistent order, thereby reducing the number of packet restarts and increasing overall efficiency.

Abstract: A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which processing has completed respectively. Upon receiving a packet start command, an entry in an active packet list is created. Upon receiving a packet done command, the active packet list is updated. The oldest done packet in the active list is retired by flushing buffered write information to a memory system. The active packet list can be used in conjunction with a system supporting speculative reads and conflict detection. In some embodiments the packet start command is inferred from a read command containing a packet identifier or sequence number.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. The packet processor implements a checkpoint repair mechanism allowing processing to restart from defined checkpoints. In some embodiments this is done with sub-sequence numbers. When a memory conflict is detected a restart signal is generated to backup and restart from a given checkpoint.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon reads and writes is recorded. Upon receiving a memory write, conflict detection logic determines if a conflict has occurred and if packet processing for a packet needs to be restarted. When such a conflict occurs, restart logic conditionally delays the restart to the packet processing engine. This can be accomplished using a stall signal or by delaying the return of the first memory read after the restart. Such a conditional delayed restart mechanism can optimize processing based on the likelihood of multiple conflicts or a single conflict.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon reads and writes is recorded. Information is maintained, including a write dependency list, allowing for the detection of memory conflicts. When a memory conflict is detected, a restart signal is generated and the entries for the associated sequence number are flushed. Further, the write dependency list is consulted to determine if other packets have been potentially corrupted and also need to be flushed. Upon detection of dependent packets that have potentially been corrupted, further packet restart signals are generated and sent to the packet processing engine.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. When a potential memory conflict is detected, the values associated with the potentially conflicting memory operations are compared. In cases where the values match, no conflict is signaled. Such a value checking mechanism reduces the number of restarts needed in certain cases.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier. Upon receiving a memory read, conflict prediction logic determines if a future conflict with a memory write is likely, and if so the processing of the memory read is delayed. After the write to which the read depends is received, the delayed memory read is allowed to complete. Such a delayed read mechanism can reduce or eliminate work discarded due to memory conflicts detected after the fact, while preserving the sequential semantics of the packet processor. The conflict prediction logic can be used in conjunction with conflict detection in which write data is buffered and information associated with both reads and writes is recorded.