Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between the packet processing engine and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. Both a strict and alternate packet ordering are evaluated, such that the semantic ordering of packets is delayed until necessary to ensure that a consistent order exists. Such a late order binding mechanism is used to allow packets to be defined in any order so long as they obey a consistent order, thereby reducing the number of packet restarts and increasing overall efficiency.

Abstract: A mechanism receives start and done commands containing packet identifiers or sequence numbers from a packet processing engine for packets for which processing is being started and for which processing has completed respectively. Upon receiving a packet start command, an entry in an active packet list is created. Upon receiving a packet done command, the active packet list is updated. The oldest done packet in the active list is retired by flushing buffered write information to a memory system. The active packet list can be used in conjunction with a system supporting speculative reads and conflict detection. In some embodiments the packet start command is inferred from a read command containing a packet identifier or sequence number.