Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon both reads and writes is recorded. Information is maintained allowing the detection of memory conflicts. The packet processor implements a checkpoint repair mechanism allowing processing to restart from defined checkpoints. In some embodiments this is done with sub-sequence numbers. When a memory conflict is detected a restart signal is generated to backup and restart from a given checkpoint.

Abstract: A mechanism receives memory reads and writes from a packet processing engine, each memory access having an associated packet identifier or sequence number. The mechanism is placed between a processing element and a memory system such that write data is buffered and information based upon reads and writes is recorded. Upon receiving a memory write, conflict detection logic determines if a conflict has occurred and if packet processing for a packet needs to be restarted. When such a conflict occurs, restart logic conditionally delays the restart to the packet processing engine. This can be accomplished using a stall signal or by delaying the return of the first memory read after the restart. Such a conditional delayed restart mechanism can optimize processing based on the likelihood of multiple conflicts or a single conflict.