Abstract: The present invention provides methods for allocating physical registers within a compiler phase to achieve efficient operation of a target CPU. The methods of the present invention allocate variables between physical registers and memory to accommodate local as well as global code structure. Such methods facilitate the location of variables that are heavily accessed at a portion of the code in a physical register during the execution thereof.
Type:
Grant
Filed:
October 13, 1994
Date of Patent:
June 25, 1996
Assignee:
Tera Computer Company
Inventors:
Brian D. Koblenz, Charles D. Callahan, II
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