Patents Assigned to Tera Probe, Inc.
  • Publication number: 20160233111
    Abstract: A method of manufacturing a semiconductor device, including steps of: (a) bonding a support plate to a first main face of a wafer, the first main face having an integrated circuit disposed thereon; (b) thinning the wafer by polishing or grinding a second main face after step (a), the second main face being opposite to the first main face; (c) dividing the wafer into multiple chip bodies concurrently with or after step (b); (d) bonding multiple reinforcing layers to second main faces of the respective chip bodies after step (c); and (e) removing the support plate after step (d).
    Type: Application
    Filed: February 4, 2016
    Publication date: August 11, 2016
    Applicant: TERA PROBE, INC.
    Inventors: Junji SHIOTA, Ichiro KONO
  • Patent number: 9343428
    Abstract: A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate.
    Type: Grant
    Filed: July 2, 2015
    Date of Patent: May 17, 2016
    Assignee: TERA PROBE, INC.
    Inventor: Shinji Wakisaka
  • Patent number: 9252099
    Abstract: Disclosed is a semiconductor device 1 comprising: a semiconductor chip 10; a multilayer wiring structure 30 stacked on the semiconductor chip 10; and an electronic component 60,80 embedded in the multilayer wiring structure 30.
    Type: Grant
    Filed: September 19, 2011
    Date of Patent: February 2, 2016
    Assignee: TERA PROBE, INC.
    Inventor: Kazuyoshi Arai
  • Publication number: 20150318244
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Application
    Filed: June 25, 2015
    Publication date: November 5, 2015
    Applicant: TERA PROBE, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20150311181
    Abstract: A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate.
    Type: Application
    Filed: July 2, 2015
    Publication date: October 29, 2015
    Applicant: TERA PROBE, INC.
    Inventor: Shinji Wakisaka
  • Publication number: 20150235845
    Abstract: According to one embodiment, a method of manufacturing a semiconductor device, includes preparing a semiconductor substrate includes a connection pad to electrically connect to a circuit element formed on a main surface, or a rewiring line connected to the connection pad, forming an insulating photosensitive resin film on the substrate with the exclusion of at least an edge portion of the substrate by inkjet, patterning the photosensitive resin film by photolithography, and forming a rewiring line, UBM or an electrode for external connection on the substrate on which the patterned photosensitive resin film is formed.
    Type: Application
    Filed: February 18, 2015
    Publication date: August 20, 2015
    Applicant: TERA PROBE, INC.
    Inventors: Nobuatsu SEKITA, Tsutomu MIYAMOTO, Norihiko KANEKO, Ichiro KONO
  • Patent number: 9105580
    Abstract: A semiconductor device includes a semiconductor construct including a semiconductor substrate and an external connection electrode provided to protrude on a surface of the semiconductor substrate, a base plate on which the semiconductor construct is installed, and a sealing layer stacked on the semiconductor substrate except for the external connection electrode and on the base plate including a side surface of the semiconductor substrate.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: August 11, 2015
    Assignee: TERA PROBE, INC.
    Inventor: Shinji Wakisaka
  • Publication number: 20150200166
    Abstract: A manufacturing method of a semiconductor device includes thermally curing a thermosetting resin material layer formed on a semiconductor wafer at a first temperature of 100° C. to 200° C. to form a protective film, preheating the semiconductor wafer having the protective film formed therein at a second temperature and removing water on the surface of the protective film, bias sputtering on the preheated semiconductor wafer, then controlling the temperature of the semiconductor wafer to a third temperature of not more than 200° C., and sputtering a material selected from the group consisting of Ti, TiW, Ta, and a conductive Ti compound to form a first conductive underlayer on the protective film.
    Type: Application
    Filed: January 15, 2015
    Publication date: July 16, 2015
    Applicant: TERA PROBE, INC.
    Inventors: Ichiro KONO, Kazufumi NOMURA, Masato FUKUSHIMA
  • Patent number: 9070638
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: June 30, 2015
    Assignee: TERA PROBE, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Publication number: 20150097302
    Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 9, 2015
    Applicant: TERA PROBE, INC.
    Inventors: Shinji WAKISAKA, Takeshi WAKABAYASHI
  • Patent number: 8946079
    Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.
    Type: Grant
    Filed: May 6, 2014
    Date of Patent: February 3, 2015
    Assignee: Tera Probe, Inc.
    Inventors: Shinji Wakisaka, Takeshi Wakabayashi
  • Publication number: 20150008579
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Application
    Filed: September 26, 2014
    Publication date: January 8, 2015
    Applicant: TERA PROBE, INC.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 8871627
    Abstract: A semiconductor device includes a semiconductor substrate on which a structure portion is provided except a peripheral portion thereof, and has a laminated structure including low dielectric films and wiring lines, the low dielectric films having a relative dielectric constant of 3.0 or lower and a glass transition temperature of 400° C. or higher. An insulating film is formed on the structure portion. A connection pad portion is arranged on the insulating film and connected to an uppermost wiring line of the laminated structure portion. A bump electrode is provided on the connection pad portion. A sealing film made of an organic resin is provided on a part of the insulating film which surrounds the bump electrode. Side surfaces of the laminated structure portion are covered with the insulating film and/or the sealing film.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: October 28, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Aiko Mizusawa, Osamu Okada, Takeshi Wakabayashi, Ichiro Mihara
  • Patent number: 8754525
    Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.
    Type: Grant
    Filed: August 6, 2013
    Date of Patent: June 17, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Shinji Wakisaka, Takeshi Wakabayashi
  • Patent number: 8749065
    Abstract: A semiconductor device includes a semiconductor substrate, a plurality of wiring lines which are provided on one side of the semiconductor substrate and which have connection pad portions, and a plurality of columnar electrodes respectively provided on the connection pad portions of the wiring lines, each of the columnar electrodes including an outer peripheral surface and a top surface. An electromigration prevention film is provided on at least the surfaces of the wiring lines. A sealing film is provided around the outer periphery surfaces of the columnar electrodes.
    Type: Grant
    Filed: January 22, 2008
    Date of Patent: June 10, 2014
    Assignee: Tera Probe, Inc.
    Inventors: Ichiro Kouno, Takeshi Wakabayashi, Ichiro Mihara