Patents Assigned to Terachip Inc.
  • Layout methodology and system for automated place and route
    Patent number: 6934924
    Abstract: A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: August 23, 2005
    Assignee: Terachip Inc.
    Inventors: Gideon Paul, Evgeny Grigoryantz
  • Layout methodology and system for automated place and route
    Publication number: 20040153985
    Abstract: A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.
    Type: Application
    Filed: May 30, 2003
    Publication date: August 5, 2004
    Applicant: TERACHIP INC.
    Inventors: Gideon Paul, Evgeny Grigoriants