Abstract: A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.

Abstract: A new simple novel Layout methodology for high integration VLSI chip is proposed, which is reduced dramatically the complexity, the cost and the schedule for implementing a complex chip such as System On a Chip (SOC) that required hierarchical layout implementation. A set of rules is provided for the place and route process.

Abstract: A method and system that provides a high processing speed and an efficient memory usage scheme includes multiple logical queues within a single physical memory. For each port of a memory device, a physical memory having slices, a free physical slice address list, and logical queues corresponding to a quality of service (QoS) classes are provided. Each logical queue includes a read pointer and a write pointer, such that a respective read and/or write operation can be performed in accordance with a logical decision that is based on an input. The logical queues manage the physical memory so that reading and writing operations are performed based on availability of free physical slices, as well as QoS. The present invention also manages reading and writing operation when all physical slices in a physical memory are filled, as well as wrap-around and jumping between physical memories.