Abstract: A method of efficiently using Transmission Control Protocol (TCP) with Acknowledgments (ACKs) comprising Selective Acknowledgement (SACK) options in asymmetrical networks by reducing the number of ACKs with SACK options to be transferred back to a sender. New ACKs with SACK options are compared to previous ACKs with SACK options as to their content, and in dependence of the comparison, i.e. if the previous ACK with a SACK option comprises redundant or invalid information and no additional information in relation to the new ACK with a SACK option, then the previous ACK with the SACK option is removed and not sent back to a sender.

Abstract: A real-time pipeline processor, which is particularly suited for VLSI implementation, is based on a hardware oriented radix-2.sup.2 algorithm derived by integrating a twiddle factor decomposition technique in a divide and conquer approach. The radix-2.sup.2 algorithm has the same multiplicative complexity as a radix-4 algorithm, but retains the butterfly structure of a radix-2 algorithm. A single-path delay-feedback architecture is used in order to exploit the spatial regularity in the signal flow graph of the algorithm. For a length-N DFT transform, the hardware requirements of the processor proposed by the present invention is minimal on both dominant components: Log4N-1 complex multipliers, and N-1 complex data memory.