Abstract: A test slot cooling system for a storage device testing system includes a storage device transporter having first and second portions. The first portion of the storage device transporter includes an air director and the second portion of the storage device transporter is configured to receive a storage device. The test slot cooling system includes a test slot housing defining an air entrance and a transporter opening for receiving the storage device transporter. The air entrance is in pneumatic communication with the air director of the received storage device transporter. The test slot cooling system also includes an air mover in pneumatic communication with the air entrance of the test slot housing for delivering air to the air director. The air director directs air substantially simultaneously over at least top and bottom surfaces of the storage device received in the storage device transporter.

Abstract: A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.

Abstract: A test system timing method simulates the timing of a synchronous clock on the device under test. Strobe pulses can be generated by routing an edge generator to delay elements with incrementally increasing delay values. A data signal or synchronous clock signal can be applied to the input of each of a set of latches which are clocked by the strobe pulses. An encoder can convert the series of samples which are thereby latched to a word representing edge time and polarity of the sampled signal. If the sampled signal is a data signal, the word can be stored in memory. If the sampled signal is a clock signal, the word is routed to a clock bus and used to address the memory. The difference between clock edge time and data edge time is provided and can be compared against expected values.

Abstract: In one embodiment, provided is a protocol specific circuit for simulating a functional operational environment into which a device-under-test is placed for functional testing. The protocol specific circuit includes a protocol aware circuit constructed to receive a non-deterministic signal communicated by a device-under-test and to control a transfer of the test stimulus signal to the device-under-test in response to the a non-deterministic signal.

Abstract: In some implementations, a method for testing is provided, which includes simulating a functional operational environment for a first type device-under-test with a tester. This includes recognizing a non-deterministic response signal having a predetermined protocol, receiving the non-deterministic response signal from the first type device-under-test, ascertaining an expected stimulus signal to be transferred to the first type device-under-test from the non-deterministic response signal based on the predetermined protocol, and initiating transmission of the expected stimulus signal to the first type device-under-test. The method further includes simulating a functional operational environment for a second type device-under-test with the tester after testing the first type device-under-test.

Abstract: An automated test equipment system includes a peripheral including first mechanical alignment features; a test head including second mechanical alignment features arranged in a pattern corresponding to the first mechanical alignment features and configured to engage the first mechanical alignment features. The automated test equipment system also includes a laser assisted alignment system including laser devices mounted to the peripheral and operable to emit laser beams; target plates mounted to the test head and including target symbols visible on surfaces of the target plates. The target symbols are arranged in a pattern corresponding to the laser devices such that, when laser beams from the laser devices are substantially aligned with the target symbols, the first mechanical alignment features are substantially aligned with the second mechanical alignment features.

Abstract: A disk drive testing system cooling circuit includes a plurality of test racks. Each of the test racks include a test slot compartment and a test electronics compartment. Each of the test slot compartments includes multiple test slots, and one or more cooling conduits configured to convey a cooling liquid toward the test slots. Each of the test electronics compartments includes test electronics configured to communicate with the test slots for executing a test algorithm, and a heat exchanger in fluid communication with the one or more cooling conduits. The heat exchanger is configured to cool an air flow directed toward the test electronics.

Abstract: According to one embodiment, a calibration system for calibrating image data produced by an imaging system is provided. The calibration system includes a processor configured for: receiving the image data from the imaging system; receiving a plurality of reference values from the imaging system; and calibrating the image data using the reference values. The reference values correspond to air image data produced by the imaging system.

Abstract: An interposer with a conductive housing is disclosed. Conductive members pass through insulators positioned in openings in the conductive housing. The conductive housing may be grounded, providing a closely spaced ground structure for signal conductors passing through the conductive housing and therefore providing a desirable impedance to signals carried by the conductive members. Such an interposer may be used in a test system to couple high speed signals between instruments that generate or measure test signals and devices under test.

Abstract: In one embodiment, an interface module is provided for connecting a plurality of signal paths to a high signal density interface. The interface module includes a board having axial conductor receptacles. The axial conductor receptacles have at least one ground via extending through the board to an interface side of the board and a shield receiving hole in the board extending into the board from a cable side of the board. At least a portion of the at least one ground via being exposed within the shield receiving hole, the shield receiving hole having a plating therein contacting the portion of the at least one ground via exposed within the shield receiving hole. The axial conductor receptacles have a plated center conductor receiving hole in the board, which extends to a signal via. The signal via extends from the center conductor hole to the interface side of the board. A non-plated hole in the board is located between the plated center conductor hole and the shield receiving hole.

Abstract: Automated test equipment for high-speed testing of devices under test (DUTs) includes a tester channel circuit generating a high-speed electrical test signal applied to the signal input terminal of each DUT, and a contacter board in physical and electrical contact with the DUTs. The contacter board has a high-speed signal transmission channel including (1) an electrical contact at which the high-speed electrical test signal is received, (2) conductive etch extending from the electrical contact to isolation areas each adjacent to the signal input terminal of a respective DUT, and (3) an embedded series isolation resistor formed on an inner layer of the contacter board at a respective isolation area forming a connection between the conductive etch and the adjacent signal input terminal of the respective DUT.

Abstract: An apparatus for use in obtaining a value from a device includes a first comparator to receive a reference high signal and a device signal, where the first comparator provides a first output signal to indicate whether the device signal is above or below the reference high signal, and a second comparator to receive a reference low signal and the device signal, where the second comparator provides a second output signal to indicate whether the device signal is above or below the reference low signal. Also included in the apparatus is circuitry (i) to adjust at least one of the reference high signal and the reference low signal based on the first output signal and the second output signal, and (ii) to output the value if a difference between the reference high signal and the reference low signal meets a predetermined criterion, the value being based on the difference.

Abstract: A system for providing a plurality of synchronous timing signals having period values that are not even multiples of the clock period including a plurality of local edge generators receiving the clock signals, each local generator including local programmable means to record an absolute time at which to generate a timing signal in the current or future period and the means to generate that timing signal at a synchronous even sub-division of the clock period resolution. A separate time value is maintained allowing generated timing signals to be delayed by more than one period. An output delay circuit generates the timing signal responsive to a future time value and a phase offset. The phase offset can be provided using a clock multiplier and serial parallel converter to simplify hardware realizations.

Abstract: A system for measuring the time interval of a signal. The second signal has a frequency higher than a frequency of the first signal. According to one embodiment, the system includes an electronic circuit for determining an approximation of the time based on a period of the second signal and for determining an adjustment to the approximation based on the second signal and a third signal corresponding to the second signal and aligned with the first signal. The length of the adjustment is less than the period of the second signal.

Abstract: A digital test instrument and a test method provide adjustable results latency. A digital test instrument includes a pattern controller configured to generate a sequence of test patterns, responsive, at least in part, to a pass/fail result, a pattern memory configured to supply the generated sequence of test patterns to a unit under test, a pattern results collection unit configured to receive at least one result value from the unit under test and to determine a pass/fail result for at least one supplied test pattern, and a synchronization unit configured to provide a no-result indication to the pattern controller during a preset number of pattern cycles following the start of a test, the preset number of pattern cycles based on a results latency of the test instrument, and to provide pass/fail results to the pattern controller after the preset number of pattern cycles.

Abstract: A reliable and durable method of testing of printed circuit boards is presented. Test access components are placed in contact regions for providing electrical connectivity between test probes and the printed circuit board. In some cases, a test access component may be a surface mount resistor. The test access component may provide two points of contact for test probes to make electrical and mechanical contact with the printed circuit board. Test access components may also provide for increased durability of testing, allowing for a greater number of test contacts to be made between test probes and printed circuit boards than were previously possible.

Abstract: A test slot cooling system for a storage device testing system includes a storage device transporter having first and second portions. The first portion of the storage device transporter includes an air director and the second portion of the storage device transporter is configured to receive a storage device. The test slot cooling system includes a test slot housing defining an air entrance and a transporter opening for receiving the storage device transporter. The air entrance is in pneumatic communication with the air director of the received storage device transporter. The test slot cooling system also includes an air mover in pneumatic communication with the air entrance of the test slot housing for delivering air to the air director. The air director directs air substantially simultaneously over at least top and bottom surfaces of the storage device received in the storage device transporter.

Abstract: A test system with multiple instruments. Some instruments act as controller instruments and others act as controlled instruments. Each instrument includes a clock generator that synthesizes one or more local clocks from a reference clock. The reference clock is a relatively low frequency clock that can be inexpensively but accurately generated and distributed to all of the instruments. A communication link between instruments is provided. Timing circuits within instruments that are to exchange time information are synchronized to establish a common time reference. Thereafter, instruments communicate time dependent commands or status messages asynchronously over the communication link by appending to each message a time stamp reflecting a time expressed relative to the common time reference. The test system includes digital instruments that contain pattern generators that send command messages to analog instruments, which need not include pattern generators.

Abstract: An automated test equipment interface system, e.g., for attaching a handler to a test head, includes a device interface board assembly. The device interface board assembly includes a stiffener frame having a frame body that is configured for attachment to a test head, alignment brackets connected to the frame body, and cam followers connected to the alignment brackets. The system also includes a docking device. The docking device includes a docking plate that is configured for attachment to a handler, pull-down ramps connected to the docking plate and movable between a retracted position and an extended position, an actuator operable to initiate movement of the pull-down ramps, and a coupling that translates movement of the actuator to corresponding movements of the pull-down ramps.

Abstract: The invention allows the interpolation factor, a critical parameter in sample rate conversion systems, to be computed in a real-time system where there is a complex relationship between a DSP clock and the data clocks. Typically, two or three of the clocks in such a system will have simple relationships (such as CLOCK1=2*CLOCK2). This relationship leads to degenerate cases where, in fact, there are only one or two clocks to consider rather than three. Furthermore, the invention allows for input data rates that are higher than the DSP clock rate. The invention also provides for an arbitrary time delay to be applied to the output signal.