Abstract: Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One embodiment of an apparatus includes a transceiver that simultaneously transmits a transmit signal and receives a receive signal. The transceiver includes a transmit DAC that generates the transmit signal based on a transmit digital signal stream. The transmit DAC includes a plurality of transmit DAC circuit elements, and a plurality of transmit DAC switches that control which of the plurality of transmit DAC circuit elements contribute to generating the transmit signal. The transceiver additionally includes an echo cancellation DAC that generates an echo cancellation signal based on the transmit digital signal stream.

Abstract: Embodiments of methods and apparatus for fast link recover are disclosed. One method includes sensing a link quality failure of a link between a receiver and a transmitter. If a link quality failure is sensed, then the receiver selects new pre-coder settings for the transmitter. The receiver communicates the new pre-coder settings to the transmitter. The transmitter applies the new pre-coder settings. The receiver computes its equalizer settings based on the new pre-coder settings of the transmitter. One apparatus or transceiver includes a means for determining a link quality failure of a link between the transceiver and a link partner transceiver. The transceiver selects new pre-coder settings for the link partner transceiver if a link quality failure is sensed. Additionally, the transceiver communicates the new pre-coder settings to the link partner transceiver, and computes its equalizer settings based on the new pre-coder settings of the link partner transceiver.

Abstract: Embodiments of methods and apparatuses for reducing electromagnetic interference in a receive signal are disclosed. One method includes receiving a receive signal. An analog cancellation signal is generated. The analog cancellation signal is summed with a receive signal, thereby mitigating electromagnetic interference in the receive signal. One apparatus includes a transceiver that includes a receive analog to digital converter (ADC) sampling a receive signal. Electromagnetic interference (EMI) processing circuitry generates an analog cancellation signal. The analog cancellation signal is summed with a receive signal, thereby mitigating electromagnetic interference in the receive signal.

Abstract: Embodiments of methods and apparatus for reducing electromagnetic interference of a received signal are disclosed. One method includes receiving a signal over at least two conductors, extracting a common-mode signal from the at least two conductors, processing the common-mode signal, and reducing electromagnetic interference of the received signal by summing the processed common-mode signal with the received signal.

Abstract: Embodiments of a method and apparatus of reducing transmit signal components of a receive signal of a transceiver are disclosed. One method includes generating a transmit signal by passing a pre-driver transmit signal through a transmit driver. An echo cancellation signal is generated by passing the pre-driver transmit signal through an echo cancellation driver. A residual echo signal is generated by passing a pre-driver residual echo cancellation signal through a residual echo cancellation driver. The transceiver simultaneously transmits the transmit signal, and receiving the receive signal. At least a portion of an echo signal of the receive signal is canceled by summing the echo cancellation signal with the receive signal. At least another portion of the cancellation echo signal of the receive signal is canceled by summing the residual echo cancellation signal with the receive signal.

Abstract: A device and method of high-speed transmission is disclosed. The method includes computing a signal quality of a received signal, the received signal being transmitted with a modulation order required by a default transmission modulation format. The signal quality is compared with a signal quality threshold required of the default transmission modulation format. If the signal quality is below the signal quality threshold, an indication of a level of signal quality failure is provided to a transmitter. The transmitter sets a number of un-coded bits within the transmission signal based upon the level of signal quality failure.

Abstract: A method and apparatus for receiving one of a plurality of Ethernet transmission protocol signals is disclosed. Each transmission protocol signal includes a plurality of transmission signal streams. The method includes determining which of the transmission protocol signals is being received. An analog front-end processor is connected to one of a plurality of protocol digital processors based on the transmission protocol signal being received. A setting of at least one functional parameter of the analog front-end processor and/or the protocol digital processors is selected based on the transmission protocol signal being received. A sampling rate of the analog front-end processor and/or a processing rate of the protocol digital processors are selected based on the transmission protocol signal being received. The plurality of transmission signal streams of the transmission protocol signal being received by the analog front-end processor are ADC sampled based on a shared clock source.

Abstract: Embodiments of a method and apparatus for a transceiver decoding an Ethernet signal. The method includes receiving an Ethernet bit stream. The bit stream is at least one of low-complexity decoded by a low-complexity decoder of the transceiver or high-complexity decoded by a high-complexity decoder of the transceiver. If the bit stream fails a low-complexity decoding test, then the bit stream is high-complexity decoded. The low-complexity decoding and high complexity decoding are iteratively repeated until the bit stream passes the low-complexity decoding test.

Abstract: An apparatus and method of aiding synchronization between a master transceiver and a slave transceiver is disclosed. The method includes the master transceiver transmitting data signals that are received by the slave transceiver. The slave transceiver locks a slave clock to the data signals with a slave phase-locked loop. The slave transceiver transmits slave clock information to the master transceiver.

Abstract: A device and method for a full-duplex transceiver is disclosed. The transceiver includes a transmitter DAC coupled to a transmission channel. The transmit DAC converting a digital transmission signal into an analog transmission signal. The transceiver further includes a receiver connected to the transmission channel. The receiver receives a desired signal and an echo signal, in which the echo signal includes at least a portion of the analog transmission signal. The receiver includes a receiver ADC, a programmable delay line for adjustably delaying a clock signal of the ADC, and a receiver processing circuit for adjusting the delay of the clock signal based at least in part upon the echo signal.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. An embodiment of a decoder includes means for generating bits representing received signals, and beliefs representing an associated reliability of each bit. A bit node computation block receives the bits and associated beliefs, and generates a plurality of bit node messages. A plurality of M serially-connected pipeline stages receive the bit node messages and after M decoding cycles, and generate a plurality of check node messages once per decoding cycle, wherein for each iteration cycle, each of the M serially-connected pipeline stages performs check node computations using all of J component codes, wherein each one of the M serially-connected pipeline stages performs check node computations once per decoding cycle using a single component code that is different that component codes used for all other of the M serially-connected pipeline stages, wherein J is at least as great as M, and wherein each iteration includes M decoding cycles.

Abstract: A device and method of setting transmit power backoff of a transceiver within a network is disclosed. The method includes estimating a channel loss of a channel of the transceiver, obtaining channel loss information, the channel loss information including estimates of channel loss of other channels of the network, obtaining crosstalk information, the crosstalk information including estimates of crosstalk between the channel and other channels of the network, and setting the power backoff based on the channel loss of the channel, the channel information, and the crosstalk information.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream. Another method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of N stages for decoding the bits, the first stage using a first of M component codes, and simultaneously executing a plurality of the N stages of decoding, each of the plurality of N stages using a different one of the M component codes.

Abstract: An device and method for a pre-sampling processing is disclosed. The pre-sampling device includes a single amplifier having a virtual ground node, and a feed back circuit connected from an output of the amplifier to the virtual ground node. The feed back circuit includes a plurality of switches connected to the virtual ground node. The switches control a plurality of programmable gain settings. The feed back circuit also includes an adjustable current source that is adjusted according to an estimated echo signal. A current of the adjustable current source is summed at the virtual ground node. The feed back circuit also includes a low pass filter that is tuned to suppress received signal frequencies above a fraction of a sampling frequency of a sampler connected to the pre-sampling device.

Abstract: Embodiments of a method and apparatus for decoding signals are disclosed. The method includes receiving modulated signals, generating bits representing the signals, and associated reliability of each bit. The method further includes executing a first stage of decoding the bits using a first component code, and simultaneously executing the first stage of decoding again using a second component code, and executing a second stage of decoding using the first component code. The first and second stages of decoding are used to generate the bit stream.

Abstract: Embodiments of an Ethernet transceiver are disclosed. The Ethernet transceiver includes a plurality of digital signal streams, at least one digital signal stream being coupled to another of the digital signal streams. A domain transformer transforms sub-blocks of each of the plurality of the digital signal streams from an original domain into a lower complexity domain. A processor joint processes the transformed sub-blocks of the digital signal streams, each joint processed digital signal stream sub-block is influenced by other digital signal streams sub-blocks. An inverse transformer inverse transforms the joint processed signal streams sub-blocks back to the original domain.

Abstract: A method and apparatus of joint processing a plurality of digital signal streams is disclosed. The method includes transforming a plurality of the digital signal streams from an original domain to a lower complexity processing domain. The transformed plurality of digital signal streams are joint processed, wherein the joint processing includes multiplying samples of the plurality of transformed digital signal streams by a processing matrix. The joint processed signal streams are inverse transformed back to the original domain. Diagonal elements of the processing matrix are adaptively selected to cancel transmission echo signals of the plurality digital signal streams introduced during transmission of the plurality digital signal streams depending upon signal coupling of the plurality of digital signal streams.

Abstract: The invention includes a full duplex transceiver for transmitting and receiving communication signals. The transceiver includes 1 to N sample and hold circuits. Each sample and hold circuit receives a first signal that includes a far-end signal, and in some cases an echo signal, and in some cases alternatively or additionally cross-talk signals. The transceiver additionally includes a plurality of subtraction circuits. Each subtraction circuit receives an output of at least one of the sample and hold circuits. Each subtraction circuit subtracts at least a fraction of a replica signal from at least a fraction of the output of the at least one of the sample and hold circuits. The subtraction circuits generate an output that represent the far-end signal with substantially reduced echo and/or cross-talk interference, and is available for additional receiver processing.

Abstract: A transceiver is disclosed. The transceiver includes a plurality of digital signal streams, wherein at least one digital signal stream is coupled to another of the digital signal streams. A transform block transforms a plurality of the digital signal streams from an original domain into a lower complexity processing domain. A processor joint processes the transformed digital signal streams, each joint processed digital signal stream being influenced by other digital signal streams. An inverse transform block inverse transforms the joint processed signal streams back to the original domain. A method of joint processing a plurality of digital signal streams is also disclosed. A first act of the method includes transforming a plurality of the digital signal streams from an original domain into a lower complexity processing domain.

Abstract: A high-speed sampling system and an analog to digital converter are disclosed. One embodiment of a method of sampling a signal includes receiving an analog signal and generating first samples at a rate of Fs, and generating second sub-samples from the first samples at a rate of Fs/N and having a relative phase of approximately (360/N)*(i?1) degrees, where i varies from 1 to N. In a first embodiment, at most two second sub-samplers are tracking the output of the first sampler at any point in time. In a second embodiment, only one of the N second sub-samplers are tracking the output of the first sampler at any point in time. A third embodiment further includes generating third samples from the second samples at a rate of Fs/N, and having a relative phase of approximately ((360/N)*(i?1)+180) degrees. A method of interleaved analog to digital converting includes corresponding time interleaved ADCs receiving the third samples.