Patents Assigned to Teranex Systems, Inc.
  • Patent number: 10158846
    Abstract: The present invention relates to conversion of 2D media to pseudo-3D left and right image pairs. In particular, it relates to imposing forced perspective on left and right versions of a 2D image. The distorted pair of images, when displayed, will be interpreted by a viewer as a 3D image. The pseudo-3D forced perspective image pairs can be produced without depth mapping of objects in scenes and without comparing the position of objects in successive image frames.
    Type: Grant
    Filed: March 30, 2011
    Date of Patent: December 18, 2018
    Assignee: TERANEX SYSTEMS, INC.
    Inventors: James F. Curtis, Shawn D. Goodwin, Christopher M. Riehl, Raymond D. Conkling
  • Patent number: 7573481
    Abstract: System and method for the management of bit plane resources are presented. Because of the scarcity of processing element (PE) memory in a SIMD architecture, it is important to ensure that it is used with optimal efficiency. The Invention discloses methods for managing PE memory at runtime such that nearly 100% utilization is achieved. The method employed allows memory to be allocated and deallocated in single bit plane increments. Runtime allocation and deallocation occurs continuously such that it is impossible to guarantee availability of contiguous blocks of PE memory. The method employed by the invention allows scattered bit planes to be used without the necessity of expending execution time to perform “garbage collection”.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: August 11, 2009
    Assignee: Teranex Systems, Inc.
    Inventor: Woodrow L. Meeker
  • Patent number: 7564462
    Abstract: System and method for reading and writing pixel aligned subframes from a frame buffer in a parallel processing system are disclosed. Optimal bandwidth access of the frame buffer requires that data be moved in bursts having multiple data words. Subframes are specified at X and Y locations within the image frame with a resolution of one pixel. In addition, subframes within a row may overlap each other and consecutive subframe rows may also overlap. Memory control logic of the invention provides pixel packing and unpacking and storing selected pixel data in a cache memory. Reading and writing to the frame buffer is provided in a manner that makes optimal use of the frame buffer internal architecture. Other capabilities of the memory control logic include decimation of pixel data during input, suppression of redundant frame buffer writes, and accessing image frame data in an interlaced manner.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: July 21, 2009
    Assignee: Teranex Systems, Inc.
    Inventors: Woodrow L. Meeker, Clara Ka Wah Sung, Carl Alan Morris