Abstract: A video-image-interpolation apparatus is provided, which includes at least three image-layering circuits, at least three motion-estimation circuits, a motion-estimation-filtering circuit, a motion-compensated frame-interpolation circuit, and a display-control circuit. Each motion-estimation circuit performs motion estimation on a reference image-layer sequence and a reference subtitle-layer sequence that are generated from an input video signal by each image-layering circuit. The motion-estimation-filtering circuit adaptively determines the motion-estimation circuit having the smallest motion error.

Abstract: A method of region-based video-image interpolation is provided, which includes the following steps: respectively dividing each image and its subsequent image in an input video signal into first regions and second regions to obtain first regional images and second regional images; performing a motion-compensated frame-interpolation process on the first regional image and the second regional image in the same position in each image and its subsequent image to obtain an interpolated regional image; performing a frame-rate-conversion process on reference images and the interpolated regional images of each first region according to an original frame rate of each first region and a display frame rate of an output video signal to obtain a regional output image of each first region; and superimposing the regional output image generated at each output timestamp by each motion-compensated frame-interpolation circuit to generate an output image of the output video signal.

Abstract: A multi-dimensional image projection apparatus is provided. The multi-dimensional image projection apparatus includes an image projector and an image-processing circuit. The image-processing circuit is configured to receive an input image, and perform a linearity transformation process and a first inverse image warping process on the input image according to sensor information about the multi-dimensional image projection apparatus relative to the projection surface to generate a first image. The image-processing circuit performs a matrix transformation process and a second inverse image warping process on the first image according to the sensor information to generate a second image, and generate an output image according to the second image. The image projector projects the output image onto the projection surface.

Abstract: A wireless charging device is provided, including an accommodating space, a first coil, a second coil, and a control module. The first coil surrounds the accommodating space, and the second coil is disposed in the accommodating space. The control module is electrically connected to the first coil and the second coil.

Abstract: A surveillance system, an image compression serializer and an image decompression deserializer are disclosed. The Surveillance System includes a video camera, a coaxial cable and a central control machine. The video camera provides a real time record and has an image compression serializer which compresses a digital image, captured by the video camera, down to a specific resolution and converts the digital image of the specific resolution into a serial format. The coaxial cable couples the image compression serializer to an image decompression deserializer of the central control machine. The digital image in the specific resolution and serial format is conveyed to the image decompression deserializer to be converted into a parallel format and decompressed to be video encoded.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The present invention is to provide a method for designing a video and image scaler based on 2-D Finite Impulse Response (FIR) filter. First, a 2-D video/image source is sampled with sampling rate higher than Nyquist rate to obtain 2-D samples; second, zeros are padded in between the 2-D samples to get a zero padding image; third, the zero padding image is passed through a 2-D FIR filter and a scaled-up image is obtained.

Abstract: The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.