Abstract: A multi-dimensional image projection apparatus is provided. The multi-dimensional image projection apparatus includes an image projector and an image-processing circuit. The image-processing circuit is configured to receive an input image, and perform a linearity transformation process and a first inverse image warping process on the input image according to sensor information about the multi-dimensional image projection apparatus relative to the projection surface to generate a first image. The image-processing circuit performs a matrix transformation process and a second inverse image warping process on the first image according to the sensor information to generate a second image, and generate an output image according to the second image. The image projector projects the output image onto the projection surface.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.

Abstract: The present invention provides a method for reducing analog PLL (Phase-lock loop) jitter in video ADC application. The HSync/CSync is replaced with a faked HSync signal to be inputted to PLL during vertical blank period. Therefore the analog PLL will only see the faked HSync signal of fixed period as a line-lock trigger signal, while no COAST signal is required. Also, the faked HSync is fine-tuned to match with the external HSync/CSync leading edge to minimize PLL jitter.

Abstract: The present invention is to provide a method for designing a video and image scaler based on 2-D Finite Impulse Response (FIR) filter. First, a 2-D video/image source is sampled with sampling rate higher than Nyquist rate to obtain 2-D samples; second, zeros are padded in between the 2-D samples to get a zero padding image; third, the zero padding image is passed through a 2-D FIR filter and a scaled-up image is obtained.

Abstract: The present invention is to provide two methods for trimming output HSync in display timing conversion for digital display application, so that the scaling controller can minimize Line Buffer timing shift and match the VSync/HSync timing requirement of digital display device. “Horizontal synchronization vibration” and “Remapping” are the two methods of the present invention.