Patents Assigned to TEREPAC
  • Patent number: 9406644
    Abstract: Parallel transfers of components from donor plates to chip modules can be performed with a single alignment step, after arranging the components to have the correct lateral positions. For example, a dimension of the chip module can be separated to be an integer multiple of a period of the component array on the donor plates.
    Type: Grant
    Filed: December 2, 2014
    Date of Patent: August 2, 2016
    Assignee: TEREPAC
    Inventors: Yun Uhm, Jayna Sheats
  • Patent number: 8759713
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process bonds multiple interconnect wires to bond pads with electrical linkages between the bond pads and then subsequently separates the adjacent bond pads.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: June 24, 2014
    Assignee: Terepac Corporation
    Inventor: Jayna Sheats
  • Publication number: 20130192523
    Abstract: The present invention discloses systems and methods for printing functional blocks from a plurality of printheads to a target substrate. In exemplary embodiments, the printing system comprises a main printhead for the majority of printing process, and a secondary printhead for supplemental printing. The system further comprises a controller, utilizing a positioning intelligence system to distribute the printing of the functional blocks between the main printhead and the secondary printhead, to minimize the motions of the printheads while maximize the printing speed.
    Type: Application
    Filed: March 4, 2013
    Publication date: August 1, 2013
    Applicant: TEREPAC CORPORATION
    Inventor: TEREPAC CORPORATION
  • Publication number: 20130193561
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Application
    Filed: March 5, 2013
    Publication date: August 1, 2013
    Applicant: TEREPAC CORPORATION
    Inventor: TEREPAC CORPORATION
  • Patent number: 8153517
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: April 10, 2012
    Assignee: Terepac Corporation
    Inventor: Jayna Sheats
  • Patent number: 8124452
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The process can separate the integrated circuits into an analog portion and a digital portion with the analog portion comprising passive components utilizing dielectric materials different than silicon dioxide and active components utilizing channel materials different than substrate single crystal silicon.
    Type: Grant
    Filed: June 14, 2009
    Date of Patent: February 28, 2012
    Assignee: TEREPAC Corporation
    Inventor: Jayna Sheats
  • Publication number: 20100313413
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The process can separate the integrated circuits into an analog portion and a digital portion with the analog portion comprising passive components utilizing dielectric materials different than silicon dioxide and active components utilizing channel materials different than substrate single crystal silicon.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100313414
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process extrudes interconnect wires over a desired location of the bond pads, and then subsequently laser cuts a correct length of the interconnect wires.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100314735
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process coats the component surfaces to facilitate the bonding of the bond pads. In another aspect, the present process coats the bond pads with shelled capsules to facilitate the bonding of the bond pads.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100315476
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process forms interconnect wires on a thermal decomposable adhesive, and after positioning the wires at proper bond pad locations, releases the interconnect wires onto the bond pads.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100314734
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process bonds multiple interconnect wires to bond pads with electrical linkages between the bond pads and then subsequently separates the adjacent bond pads.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100314719
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides multiple interconnect wires in the form of a ribbon between the bond pads, and then subsequently separates the ribbon into multiple individual interconnect wires.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100314718
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. In another embodiment, the present chip assembling provides high density interconnect wires between bond pads, enabling cost-effective assembling of small chip components. In an aspect, the present process provides a beveled slope of the components to facilitate interconnection bonding.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100314751
    Abstract: The present invention discloses methods and apparatuses for the separations of IC fabrication and assembling of separated IC components to form complete IC structures. In an embodiment, the present fabrication separation of an IC structure into multiple discrete components can take advantages of dedicated IC fabrication facilities and achieve more cost effective products. The present process can fabricate multiple components separately before assembling them into a complete integrated circuit. In an aspect, the ready-for-assembling components are taken directly from processed wafers without any additional assembling processes, and/or having lateral dimensions less than 1 mm.
    Type: Application
    Filed: June 14, 2009
    Publication date: December 16, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats
  • Publication number: 20100255179
    Abstract: The present invention discloses systems and methods for printing functional blocks from a plurality of printheads to a target substrate. In exemplary embodiments, the printing system comprises a main printhead for the majority of printing process, and a secondary printhead for supplemental printing. The system further comprises a controller, utilizing a positioning intelligence system to distribute the printing of the functional blocks between the main printhead and the secondary printhead, to minimize the motions of the printheads while maximize the printing speed.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Applicant: TEREPAC
    Inventors: Douglas Knox, Jayna Sheats, Ric Asselstine
  • Publication number: 20100252186
    Abstract: The present invention relates to methods and apparatuses for assembling substrates with functional blocks, using a printhead to deliver individual functional blocks to the appropriate locations on the substrates. In an embodiment, the functional block releasing mechanism comprises a heat source to provide thermal energy and a light source to provide photon energy, wherein the heat source and the light source enable releasing individual functional blocks from the reservoir for positioning on the substrate. The heat source can comprise an array of heating elements, such as thin film heating elements, which can provide localized heating to individual elements, thus enabling releasing individual functional blocks. The light source can comprise a laser beam and a moving mechanism to move the laser beam to the individual functional blocks.
    Type: Application
    Filed: April 6, 2009
    Publication date: October 7, 2010
    Applicant: TEREPAC
    Inventor: Jayna Sheats