Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.

Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.

Abstract: “Shoot-through” timing failures in a scan chain of a defective semiconductor integrated circuit corrupt test pattern data used to perform failure analysis. Methods and procedures are provided to detect “shoot-through” conditions, determine the number of shoot-through scan cells, and to determine the location of the shoot-through cells within a scan chain. Reset test pattern results can be analyzed to identify candidate locations of shoot-through cells and when combined with candidate cell locations from analysis of physical clock distribution trees and potential clock-skew issues, the exact location of all shoot-through cells can be determined. Methods are also provided to use shoot-through cell locations to identify the defective clock net containing the physical defect causing the clock skew conditions needed to produce shoot-through timing failures.

Abstract: Automated test procedures, carried out under software control, can be employed to test a device, testing individual pins, and/or groups of pins, to detect and diagnose or characterize various types of failures. A distributed FA system includes a shared database for device definitions, test setups, and test results. Test platforms provide I/O curve tracing which can provide both a qualitative visual representation and a quantitative measured performance. The disclosed system enables and exploits front line testing of devices in the field. Response to the customer can be nearly immediate. Eliminate “false returns” by differentiation of use versus a real quality issue.

Abstract: Various embodiments related to identifying a candidate defect region in a semiconductor device are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; generating a physical representation of portion of a logical design of the semiconductor device, the physical representation including location information for physical instantiations of logical cells and logical interconnections included in the portion of the logical design; identifying a suspect logical region in the physical representation, the suspect logical region including a portion of the logical cells and the logical interconnections electrically connected with the scan chain; generating a candidate defect region within the semiconductor device, the candidate defect region being defined, via the physical representation, to include the physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: A chip diagnostics management system includes secure design information that define production features of integrated circuit devices and are accessible according to selected levels of access privilege. A database of device defect information includes information of defects of devices produced according to the production features of the design information and associated wafers, production lots, and dies in or with which the devices were produced. A diagnostic manager correlates device defect information from plural wafers with the design information to identify a device location with a probability of being associated with the device defect information. A diagnostic manager viewer indicates the device location together with an amount of design information correlated the level of access privilege assigned to a selected user.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. A method for identifying a reference scan cell is provided, the method including, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The method further includes, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. A method for identifying a reference scan cell is provided, the method including, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The method further includes, in a shift mod, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: Embodiments related to identifying a reference scan cell locationally related to a fault condition exhibited by a scan chain in which the reference scan cell is included are provided. In one example, a method for identifying a reference scan cell is provided, the method comprising, in a capture mode, outputting combinational logic values to scan cells in the scan chain so that scan cell values for the scan cells are based on respective combinational logic values, the combinational logic values electrically connected with the scan chain. The example method further comprises, in a shift mode, sequentially determining the scan cell value for each scan cell, and identifying as the reference scan cell a scan cell last determined to be at an expected logical state for that scan cell.

Abstract: Embodiments related to electrically characterizing a semiconductor device are provided. In one example, a method for characterizing a pin of a semiconductor device is provided, the method comprising providing a test pattern to the semiconductor device. Further, the method includes adjusting a selected electrical state of a pin of the semiconductor device and measuring a value for a dependent electrical state of the pin responsive to the selected electrical state. The example method also includes generating an electrical characterization for the pin by correlating the dependent electrical state with the selected electrical state and outputting the electrical characterization for display.

Abstract: Various embodiments related to correlating a location of a defect on a substrate for a semiconductor device to an electrical significance of a device structure at that location are disclosed. For example, one embodiment includes receiving a defect location for the location on the substrate where the defect was detected; receiving a physical representation of the semiconductor device for the defect location; generating a significance determination indicating whether the defect is located in an electrically significant region by correlating the defect location to logical and physical layout information included in the physical representation; and displaying the significance determination.

Abstract: Various embodiments related to identifying regions including physical defects in semiconductor devices are disclosed. For example, one embodiment includes receiving an electrical test mismatch reported for a scan chain; identifying a suspect logical region including a plurality of logic cones electrically connected with the scan chain; adjusting a scope of the suspect logical region by simulating data flow within the logic cones, generating simulated scan chain output based on the simulated data flow within the logic cones, and excluding at least one of the logic cones from the suspect logical region based on a comparison of the electrical test mismatch and the simulated scan chain output; after adjusting the scope of the suspect logical region, generating a candidate defect region, the candidate defect region being defined to include physical instantiations of logical cells and logical interconnections included in the suspect logical region; and displaying the candidate defect region.