Patents Assigned to Tessera, Inc
  • Patent number: 10847639
    Abstract: Described herein is a FinFET device in which epitaxial layers of semiconductor material are formed in source/drain regions on fin portions. The fin portions can be located within a dielectric layer that is deposited on a semiconductor substrate. Surfaces of the fin portions can be oriented in the {100} lattice plane of the crystalline material of the fin portions, providing for good epitaxial growth. Further described are methods for forming the FinFET device.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: November 24, 2020
    Assignee: Tessera, Inc.
    Inventors: Kangguo Cheng, Juntao Li
  • Patent number: 10832952
    Abstract: A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: November 10, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin D. Briggs, Jessica Dechene, Elbert E. Huang, Joe Lee, Theodorus E. Standaert
  • Patent number: 10833044
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: November 10, 2020
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Patent number: 10825689
    Abstract: A method of fabricating semiconductor fins, including, patterning a film stack to produce one or more sacrificial mandrels having sidewalls, exposing the sidewall on one side of the one or more sacrificial mandrels to an ion beam to make the exposed sidewall more susceptible to oxidation, oxidizing the opposite sidewalls of the one or more sacrificial mandrels to form a plurality of oxide pillars, removing the one or more sacrificial mandrels, forming spacers on opposite sides of each of the plurality of oxide pillars to produce a spacer pattern, removing the plurality of oxide pillars, and transferring the spacer pattern to the substrate to produce a plurality of fins.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: November 3, 2020
    Assignee: Tessera, Inc.
    Inventor: Kangguo Cheng
  • Patent number: 10818759
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: October 27, 2020
    Assignee: Tessera, Inc.
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A. Vega
  • Patent number: 10804151
    Abstract: In interconnect fabrication (e.g. a damascene process), a barrier layer (possibly conductive) is formed over a substrate with holes, a conductor is formed over the barrier layer, and the conductor and the barrier layer are polished to expose the substrate around the holes and provide interconnect features in the holes. To prevent erosion/dishing of the conductor over the holes, the conductor is covered by another, “first” layer before polishing; then the first layer, the conductor, and the barrier layer are polished to expose the substrate. The first layer may or may not be conductive. The first layer protects the conductor to reduce or eliminate the conductor erosion/dishing over the holes.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 13, 2020
    Assignee: Tessera, Inc.
    Inventors: Cyprian Emeka Uzoh, Vage Oganesian, Ilyas Mohammed
  • Patent number: 10804147
    Abstract: A semiconductor interconnect structure that has a first portion included in an upper interconnect level and a second portion included in a lower interconnect level. The semiconductor interconnect structure has a segment of dielectric capping material that is in contact with the bottom of the first portion, which separates, in part, the upper interconnect level from a lower interconnect level. The second portion is in electrical contact with the first portion.
    Type: Grant
    Filed: November 20, 2019
    Date of Patent: October 13, 2020
    Assignee: Tessera, Inc.
    Inventors: Conal E. Murray, Chih-Chao Yang
  • Patent number: 10804193
    Abstract: Embodiments are directed to a semiconductor structure having a dual-layer interconnect and a barrier layer. The interconnect structure combines a first conductive layer, a second conductive layer, and a barrier layer disposed between. The result is a low via resistance combined with improved electromigration performance. In one embodiment, the first conductive layer is copper, the second conductive layer is cobalt, and the barrier layer is tantalum nitride. A barrier layer is not used in other embodiments. Other embodiments are also disclosed.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: October 13, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin D. Briggs, Takeshi Nogami, Raghuveer R. Patlolla
  • Patent number: 10770347
    Abstract: Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: September 8, 2020
    Assignee: Tessera, Inc.
    Inventors: Daniel C. Edelstein, Son V. Nguyen, Takeshi Nogami, Deepika Priyadarshini, Hosadurga K. Shobha
  • Patent number: 10763326
    Abstract: A method of forming a semiconductor structure includes forming a middle-of-line (MOL) oxide layer in the semiconductor structure. The MOL oxide layer including multiple gate stacks formed on a substrate. A nitride layer is formed over a silicide in the MOL oxide layer. At least one self-aligned contact area (CA) element is formed within the nitride layer. The MOL oxide layer is selectively recessed on a first side and a second side of the at least one self-aligned CA element leaving remaining portions of the MOL oxide layer on the nitride layer and a nitride. A nitride cap of the plurality of gate stacks is selectively recessed. An air-gap oxide layer is deposited for introducing one or more air-gaps in the deposited air-gap oxide layer. The air gap oxide layer is reduced to the at least one self-aligned CA element and the nitride layer.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 1, 2020
    Assignee: Tessera, Inc.
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. V. S. Surisetty
  • Patent number: 10763166
    Abstract: An etch back air gap (EBAG) process is provided. The EBAG process includes forming an initial structure that includes a dielectric layer disposed on a substrate and a liner disposed to line a trench defined in the dielectric layer. The process further includes impregnating a metallic interconnect material with dopant materials, filling a remainder of the trench with the impregnated metallic interconnect materials to form an intermediate structure and drive-out annealing of the intermediate structure. The drive-out annealing of the intermediate structure serves to drive the dopant materials out of the impregnated metallic interconnect materials and thereby forms a chemical- and plasma-attack immune material.
    Type: Grant
    Filed: January 17, 2019
    Date of Patent: September 1, 2020
    Assignee: Tessera, Inc.
    Inventors: Benjamin D. Briggs, Elbert Huang, Takeshi Nogami, Christopher J. Penny
  • Publication number: 20200273947
    Abstract: A capacitor includes a stack. The stack has a first metallic layer formed over a substrate, an insulator formed over the first metallic layer, and a second metallic layer formed over the insulator. The first metallic layer has at least one high domain and at least one low domain, where a surface of the substrate in the at least one low domain has a height that is lower than a surface of the substrate in the at least one high domain.
    Type: Application
    Filed: May 11, 2020
    Publication date: August 27, 2020
    Applicant: Tessera, Inc.
    Inventors: Kisup Chung, Isabel C. Estrada-Raygoza, Hemanth Jagannathan, Chi-Chun Liu, Yann A.M. Mignot, Hao Tang
  • Publication number: 20200266066
    Abstract: Methods of forming fins include masking a region on a three-color hardmask fin pattern, leaving a fin of a first color exposed. The exposed fin of the first color is etched away with a selective etch that does not remove fins of a second color or a third color. The mask and all fins of a second color are etched away. Fins are etched into a fin base layer using the fins of the first color and the fins of the third color.
    Type: Application
    Filed: February 24, 2020
    Publication date: August 20, 2020
    Applicant: TESSERA, INC.
    Inventors: John C. Arnold, Anuja E. DeSilva, Nelson M. Felix, Chi-Chun Liu, Yann A.M. Mignot, Stuart A. Sieg
  • Publication number: 20200266072
    Abstract: First lithography and etching are carried out on a semiconductor structure to provide a first intermediate semiconductor structure having a first set of surface features corresponding to a first portion of desired fin formation mandrels. Second lithography and etching are carried out on the first intermediate structure, using a second mask, to provide a second intermediate semiconductor structure having a second set of surface features corresponding to a second portion of the mandrels. The second set of surface features are unequally spaced from the first set of surface features and/or the features have different pitch. The fin formation mandrels are formed in the second intermediate semiconductor structure using the first and second sets of surface features; spacer material is deposited over the mandrels and is etched back to form a third intermediate semiconductor structure having a fin pattern. Etching is carried out on same to produce the fin pattern.
    Type: Application
    Filed: February 20, 2020
    Publication date: August 20, 2020
    Applicant: Tessera, Inc.
    Inventors: Fee Li Lie, Dongbing Shao, Robert Wong, Yongan Xu
  • Publication number: 20200266284
    Abstract: A method and structures are used to fabricate a nanosheet semiconductor device. Nanosheet fins including nanosheet stacks including alternating silicon (Si) layers and silicon germanium (SiGe) layers are formed on a substrate and etched to define a first end and a second end along a first axis between which each nanosheet fin extends parallel to every other nanosheet fin. The SiGe layers are undercut in the nanosheet stacks at the first end and the second end to form divots, and a dielectric is deposited in the divots. The SiGe layers between the Si layers are removed before forming source and drain regions of the nanosheet semiconductor device such that there are gaps between the Si layers of each nanosheet stack, and the dielectric anchors the Si layers. The gaps are filled with an oxide that is removed after removing the dummy gate and prior to forming the replacement gate.
    Type: Application
    Filed: February 21, 2020
    Publication date: August 20, 2020
    Applicant: Tessera, Inc.
    Inventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, John R. Sporre, Sean Teehan
  • Publication number: 20200259002
    Abstract: A method of forming a semiconductor device that includes forming a fin structure from a bulk semiconductor substrate and forming an isolation region contacting a lower portion of a sidewall of the fin structure, wherein an upper portion of the sidewall of the fin structure is exposed. A sacrificial spacer is formed on the upper portion of the sidewall of the fin structure. The isolation regions are recessed to provide an exposed section of the sidewall of the fin structure. A doped semiconductor material is formed on the exposed section of the lower portion of the sidewall of the fin structure. Dopant is diffused from the doped semiconductor material to a base portion of the fin structure.
    Type: Application
    Filed: April 14, 2020
    Publication date: August 13, 2020
    Applicant: Tessera, Inc.
    Inventors: Veeraraghavan S. Basker, Zuoguang Liu, Tenko Yamashita, Chun-chen Yeh
  • Patent number: 10741449
    Abstract: A semiconductor device includes a first gate stack arranged about a first nanowire and a second nanowire, the first nanowire is arranged above a second nanowire, the first nanowire is connected to a first source/drain region and a second source/drain region. A second gate stack is arranged about a third nanowire and a fourth nanowire, the third nanowire is arranged above a fourth nanowire, the third nanowire is connected to a third source/drain region and a fourth source/drain region. An insulator layer having a first thickness is arranged adjacent to the first gate stack.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: August 11, 2020
    Assignee: Tessera, Inc.
    Inventors: Kangguo Cheng, Lawrence A. Clevenger, Balasubramanian S. Pranatharthiharan, John Zhang
  • Patent number: 10734492
    Abstract: An asymmetric high-k dielectric for reduced gate induced drain leakage in high-k MOSFETs and methods of manufacture are disclosed. The method includes performing an implant process on a high-k dielectric sidewall of a gate structure. The method further includes performing an oxygen annealing process to grow an oxide region on a drain side of the gate structure, while inhibiting oxide growth on a source side of the gate structure adjacent to a source region.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: August 4, 2020
    Assignee: Tessera, Inc.
    Inventors: Anthony I. Chou, Arvind Kumar, Chung-Hsun Lin, Shreesh Narasimha, Claude Ortolland, Jonathan T. Shaw
  • Publication number: 20200243648
    Abstract: Semiconductor devices include a first semiconductor fin. A first gate stack is formed over the first semiconductor fin. Source and drain regions are formed on respective sides of the first gate stack. An interlayer dielectric is formed around the first gate stack. A gate cut plug is formed from a dielectric material at an end of the first gate stack.
    Type: Application
    Filed: February 21, 2020
    Publication date: July 30, 2020
    Applicant: TESSERA, INC.
    Inventors: John R. Sporre, Siva Kanakasabapathy, Andrew M. Greene, Jeffrey Shearer, Nicole A. Saulnier
  • Patent number: 10727315
    Abstract: Inner and outer spacers for nanosheet transistors are formed using techniques that improve junction uniformity. One nanosheet transistor device includes outer spacers and an interlevel dielectric layer liner made from the same material. A second nanosheet transistor device includes outer spacers, inner spacers and an interlevel dielectric layer liner that are all made from the same material.
    Type: Grant
    Filed: January 20, 2019
    Date of Patent: July 28, 2020
    Assignee: Tessera, Inc.
    Inventors: Kangguo Cheng, Juntao Li, Heng Wu, Peng Xu