Abstract: An instrument comprises an odd multiplexer (11o) for sequentially selecting terminals connected to odd wires one by one, an even multiplexer (11e) for sequentially selecting terminals connected to even wires on by one, odd relay switches (13o-1, 13o-2) for switching connection of the odd multiplexer (11o) to a ground terminal, and even relay switches (11e-1),11e-2) for switching connection of the even multiplexer (11e) to a ground terminal. The multiplexers are operated at high speed in such a way that when one of the relay switches does not select connection to the ground terminal, and other selects connection to the ground terminal. By using such multiplexers, wires are sequentially selected at high speed, and the wire adjacent to the selected wire is grounded by the relay switch. While thus switching, the potential appearing at an input terminal (2) of a multiplexer is measured. In this way, an open test and a short test of wiring can be made at high speed.

Abstract: Relay switches are provided between the output terminals of multiplexers in a certain layer in a tree structure and an input terminal of a multiplexer in a layer that is one level higher than the certain layer; the relay switch connected to the multiplexer, among the multiplexers in the certain layer, that is involved in selecting a signal is turned ON and the relay switches connected to the other multiplexers are turned OFF, whereby the resistance components and the capacitance components of the multiplexers whose corresponding relay switches have been turned OFF can be disconnected from the tree structure, thereby reducing the value of the time constant CR that affects the operating speed of the multiplexer. As a result, the disadvantage that the increase in the time constant decelerates the operating speed of the entire multiplexer circuit can be suppressed.

Abstract: There are included a mother board (11), which has therein a multiplexer and a test pass/fail determining part, and a daughter board (12) that has therein an A/D converting part and an averaging part. The mother board (11) multiplexes a plurality of analog signals outputted from a plurality of output terminals of an LSI formed on a wafer (W) to be tested, thereby reducing the number of signals in an early stage. The daughter board (12) A/D converts and averages the resultant signals from the mother board (11), and supplies the averaged characteristic measured data to the mother board (11) for a pass/fail determination. This can eliminate the need for a large number of parallel transmission paths and processing circuits, raise the throughput, and reduce the affections of noise included in the analog signals due to the average processing.

Abstract: A display device drive device includes a signal processing section (20) for correcting an input digital image signal and outputting a digital corrected signal, an analog signal output section (30) for outputting an analog image signal to a plurality of image output terminals (1), a signal switching selection (40) for successively selecting an analog image signal from the analog signal output section (30), and a delta/sigma modulator (9) for delta/sigma-modulating the analog image signal selected by the signal switching section (40) and feedback-inputs the created 1-bit digital modulated signal to the signal processing section (20). The signal processing section (20) successively outputs initial output data Vinit0 to Vinitm to the analog signal output section (30), receives a modulated signal for the initial output data Vinit0 to Vinitm from the delta/sigma modulator (9) so as to calculate correction data.

Abstract: A drive device includes an analog signal output part (30) for outputting analog image signals to the respective ones of a plurality of image output terminals (1); a signal switch part (40) for sequentially selecting analog image signals from the analog signal output part (30); and a delta-sigma modulator (9) for delta-sigma modulating the analog image signals selected by the signal switch part (40) and for outputting a 1-bit digital modulated signal from a delta-sigma modulation output terminal (2). The delta-sigma modulator (9) converts the analog image signals outputted from the multiple image output terminals (1) to the 1-bit digital modulated signal, which can be extracted, as a test signal, from the delta-sigma modulation output terminal (2) to the exterior via a single wire.