Abstract: A display system includes a light source 110 and a spatial light modulator 122 located to receive light from the light source. The spatial light modulator (e.g., a DMD) includes a number of independently controllable elements that are activated for a period of time to display light of a desired brightness. A light sensor 136 is located to determine a characteristic of light from the light source 110. A control circuit 126 is coupled to the spatial light modulator 122 and controls the period of time that the independently controllable elements are activated. This period of time is based at least in part by an input received from the light sensor 136.

Abstract: A differential input comparator circuit comprises an input stage comprising dual polarity input voltages and an output stage adapted to output a differential voltage based on the input voltages, wherein the differential voltage is adapted to be transmitted to a comparator and wherein the circuit has high input impedance and works with high input voltage swings.

Abstract: A system for detecting liquid flow from a nozzle in a semiconductor processing device includes a first fiber optic sensor, a second fiber optic sensor, and an amp. The first fiber optic sensor and second fiber optic sensor are located on opposite sides of at least one nozzle. The first fiber optic sensor transmits light, and the second fiber optic sensor receives more of the light when the nozzle is not dispensing liquid than when the nozzle is dispensing liquid. The amp is coupled to the first fiber optic sensor and second fiber optic sensor. The amp indicates whether the nozzle is dispensing liquid according to an amount of the light received at the second fiber optic sensor.

Abstract: An analog-to-digital converter device capable of measuring inputs beyond a supply voltage including: an N bit analog-to-digital converter powered by a supply voltage and a reference voltage; a range resolution stage capable of receiving inputs at higher voltages than the supply voltage, providing an input to the analog-to-digital converter, and outputting a logic value of one for the N+1th bit in response to an input signal higher than the reference voltage; and a bootstrapped input multiplexer stage for connecting low voltage input signals directly to the analog-to-digital converter and for connecting input signals that can exceed the supply voltage to the range resolution stage.

Abstract: A method (100) of fabricating an electronic device (200) formed on a semiconductor wafer. The method forms a layer (215) of a first material in a fixed position relative to the wafer. The first material has a dielectric constant less than 3.6. The method also forms a photoresist layer in (216) a fixed position relative to the layer of the first material. The method also forms at least one void (220) through the layer of the first material in response to the photoresist layer. Further, the method subjects (106) the semiconductor wafer to a plasma which incorporates a gas which includes hydrogen so as to remove the photoresist layer.

Abstract: The present invention provides, in one aspect, a method of designing an integrated circuit. In this particular aspect, the method comprises reducing soft error risk in an integrated circuit by locating a structure, relative to a node of the integrated circuit to reduce a linear energy transfer associated with a sub-atomic particle, into the node, such that the linear energy transfer does not exceed a threshold value associated with the integrated circuit.

Abstract: A high speed parser containing a content addressable memory (CAM) providing select values to multiplexers. The CAM is programmed to implement search rules which examine input data for specific semantics according to a protocol, and outputs the specific bit positions at which the corresponding desired data units are present. The outputs are provided to multiplexers to cause the desired data units to be selected on the corresponding output paths of the multiplexors.

Abstract: According to one embodiment of the present invention, a method for color illumination for an image display system includes field sequentially operating an array of emitters to generate a sequence of light beams. Each light beam includes one color. A first light beam of a first color is combined with a second light beam of a second color. The first and second light beams are combined in an optical path to travel concurrently. The combination of the first and second light beams results in a composite color coordinate. The combination of the first and second light beams are directed at a spatial light modulator operable to receive the combination and produce a desired color on a display.

Abstract: An integrated preamplifier circuit for detecting a signal current from a photodiode and converting the signal current into an output voltage is provided. The circuit includes a signal amplifier and a dummy amplifier, the dummy amplifier being matched to the signal amplifier. Each of these amplifiers includes an input transistor and an output transistor, the input transistor of the signal amplifier receiving an input signal derived from the signal current and the input transistor of the dummy amplifier receiving no input signal. The signal and dummy amplifiers provide the desired differential output signal. The input transistors of the signal and dummy amplifiers each have a biasing current source forced to follow a reference current source implemented within the integrated circuit.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: Embodiments of the invention provide a method for selectively identifying nodes implemented enhanced version of a standard by creating a random locally administered MAC address and advertising said random locally administered MAC address as the address that implies a particular amendment of a standard.

Abstract: A wireless device in a wireless network transmits a data frame even in the presence of in-band interference (from transmission of other devices) on a shared channel provided in the wireless network. In an embodiment, configuration data is provided to the wireless device indicating whether frames be transmitted (stomped) or not in the presence of such inband interference. If the configuration data indicates that the wireless device transmit in the presence of in-band interference, the wireless device transmits a frame if the transmitter of the interfering communication is determined to be from a different basic service set (BSS).

Abstract: Described is a rear projection television with reduced cabinet depth and method of manufacturing thereof. An anamorphic projection lens compresses an image and projects it along an optic path, where a cylindrical mirror expands and reflects the image within the optic path. The combination of compression and expansion facilitates in the design of a rear projection television with reduced cabinet depth.

Abstract: The present invention facilitates semiconductor fabrication by maintaining shape and density of an etch stop layer (206) during trench fill operations. The shape and density of the etch stop layer (206) is maintained by forming a protective alloy liner layer (310) on the etch stop layer (206) prior to trench fill operations. The protective alloy liner (310) is comprised of an alloy that is resistant to materials employed in the trench fill operations. As a result, clipping and/or damage to the etch stop layer (206) is mitigated thereby facilitating a subsequent planarization process that employs the etch stop layer (206). Additionally, selection of thickness and composition (1706) of the formed protective alloy (310) yields a stress amount and type (1704) that is applied to channel regions of unformed transistor devices, ultimately providing for an improvement in channel mobility.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A method of forming a film stack in an integrated circuit, said method comprising depositing a layer of silicon carbide adjacent a first layer of dielectric material, depositing a layer of silicon nitride adjacent the layer of silicon carbide, and depositing a second layer of dielectric material adjacent the layer of silicon nitride.

Abstract: A method (100) of forming a transistor includes forming a gate structure (106, 108) over a semiconductor body and forming recesses (112) substantially aligned to the gate structure in the semiconductor body. Carbon-doped silicon is then epitaxially grown (114) in the recesses, followed by forming sidewall spacers (118) over lateral edges of the gate structure. The method continues by implanting source and drain regions in the semiconductor body (120) after forming the sidewall spacers. The carbon-doped silicon formed in the recesses resides close to the transistor channel and serves to provide a tensile stress to the channel, thereby facilitating improved carrier mobility in NMOS type transistor devices.

Abstract: A voltage generation circuit generates a reference voltage using a bandgap reference. A countering circuit is included to adaptively counter for any deviations caused in a bandgap reference voltage such that the reference voltage is independent of fabrication process variations and changes in ambient temperature. In an embodiment, current, proportionate to deviation in absolute value of Vbe from a nominal value, is injected into an emitter-base junction to cause Vbe to equal the nominal value.

Abstract: A packaged micromechanical device (100) having a blocking material (116) encapsulating debris-generating regions thereof. The blocking material (116) prevents the generation of debris that could interfere with the operation of the micromechanical device (100). Debris-generating regions of the device (100), including debris-creating sidewalls and any debris-harboring cavities, as well as electrical connections (108) linking the device (100) to the package substrate (102) are encapsulated by the blocking material (116). The blocking material (116) avoids contact with any debris-intolerant regions (118) of the device (100). A package lid (124), which is glass in the case of many DMD packages, seals the device (100) in a package cavity (120).

Abstract: A nonvolatile memory array is encased in a P-well, and the P-well encased in a deep N-well, the two wells separating the memory array from the integrated circuit substrate and from the other circuitry of the integrated circuit. At the same time the deep N-well is formed for the nonvolatile memory array, deep N-wells are formed for the high-voltage P-channel transistors of the logic circuitry. At the same time the P-well is formed for the nonvolatile memory array, P-wells are formed for the low-voltage N-channel transistors. The memory array contains nonvolatile cells of the type used in the ultra-violet-erasable EPROMs. During erasure, the isolated-well formation allows the source, the drain and the channel of selected cells to be driven to a positive voltage. The isolated well is also driven to a positive voltage equal to, or slightly greater than, the positive voltage applied to the source and drain, thus eliminating the field-plate breakdown-voltage problem.