Abstract: A circuit comprises a first set of serially-connected inverters comprising an input port, the first set of serially-connected inverters comprising a first subset of serially-connected inverters, the first subset of serially-connected inverters odd in number and comprising an input port and an output port; a first low-pass filter comprising an input port coupled to the output port of the first subset of serially-connected inverters, and an output port; a second low-pass filter comprising an input port coupled to the input port of the first subset of serially-connected inverters, and an output port; and a first differential amplifier comprising a first input port coupled to output port of the first low-pass filter, a second input port coupled to the output port of the second low-pass filter, and an output port coupled to the input port of the first set of serially-connected inverters.

Abstract: In described examples, an image-generating panel is arranged for modulating a projection beam to include a modulated optical image. A cooling device is arranged to transfer heat received from the image-generating panel to a heat sink. The cooling device is arranged to receive the projection beam on a first side and to transmit the projection beam from a second side. The heat received from the image-generating panel can include heat generated by the image-generating panel in response to incidental sunlight.

Abstract: A stream of data is accessed from a memory system using a stream of addresses generated in a first mode of operating a streaming engine in response to executing a first stream instruction. A block cache management operation is performed on a cache in the memory using a block of addresses generated in a second mode of operating the streaming engine in response to executing a second stream instruction.

Abstract: A method of forming a functionalized sensor array includes providing a substrate having at least one sensor array chip including a plurality of sensor structures. The sensor structures include a piezoelectric layer interposed between upper and lower electrodes and positioned across an area of the sensor array chip in a spatial arrangement. An inkjet cartridge chip is also provided having a plurality of microfluidic channels including a fill side having a plurality of fill side orifices and a dispense side having a plurality of dispense nozzles, wherein two or more of the plurality of microchannels are loaded with different sensing materials, and wherein locations of the plurality of dispense nozzles are matched to the spatial arrangement. The plurality of dispense nozzles are aligned to the plurality of sensor structures, and the plurality of dispense nozzles are actuated to deposit the different sensing materials on the plurality of sensor structures.

Abstract: A delta sigma modulator with an input stage and an output stage. The input stage receives an analog input signal and an output of a first digital to analog converter (DAC). The input stage generates a processed error signal. An additional summation device receives the processed error signal. The output stage receives an output of the additional summation device and generates a delayed digital output signal. A differentiator and the first digital to analog converter (DAC) receive the delayed digital output signal as a feedback signal. A second DAC receives an output of the differentiator and provides an output to an additional negative feedback coefficient multiplier. The additional summation device receives an output of the additional negative feedback coefficient multiplier.

Abstract: An integrated circuit may be formed by removing source/drain spacers from offset spacers on sidewalls of MOS transistor gates, forming a contact etch stop layer (CESL) spacer layer on lateral surfaces of the MOS transistor gates, etching back the CESL spacer layer to form sloped CESL spacers on the lateral surfaces of the MOS transistor gates with heights of ¼ to ¾ of the MOS transistor gates, forming a CESL over the sloped CESL spacers, the MOS transistor gates and the intervening substrate, and forming a PMD layer over the CESL.

Abstract: A system on a package (SOP) can include a galvanic isolator. The galvanic isolator can include an input stage configured to transmit an input RF signal in response to receiving an input modulated signal. The galvanic isolator can also include a resonant coupler electrically isolated from the input stage by a dielectric. The resonant coupler can be configured to filter the input RF signal and transmit an output RF signal in response to the input RF signal. The galvanic isolator can further include an output stage electrically isolated from the resonant coupler by the dielectric. The output stage can be configured to provide an output modulated signal in response to receiving the output RF signal.

Abstract: In accordance with at least some embodiments, a system includes a processing entity configured to run multiple threads. The system also includes a direct memory access (DMA) engine coupled to the processing entity, the DMA engine being configured to track DMA in-flight status information for each of a plurality of DMA channels. The processing entity is configured to manage overlapping DMA requests to a DMA channel of the DMA engine based on said DMA in-flight status information.

Abstract: The disclosed systems and methods of low offset switched capacitor comparator reduce settling errors. The system operates in two major phases. During a first phase, the input voltage is sampled on the input capacitors and a differential amplifier is configured in a unity gain configuration to sample the amplifier offset. During the second phase, the input voltage difference is amplified at the output of the comparator. The amplifier transient sampling error is reduced by shorting the outputs of the differential amplifier for a shorting period at the start of the second phase. A clocked comparator at the output of the differential amplifier provides a fast comparison using internal positive feedback. The differential amplifier should have developed sufficient differential output voltage to overcome the offset of the clocked comparator.

Abstract: A method of transmitting signals in a communication system over at least two time periods including generating a base signal comprising of at least two samples in each time period, selecting a scrambling sequence of length equal to or greater than the number of time periods, scaling all samples in said signal in a time period with one element of said scrambling sequence and transmitting the scaled signal in said time period. Different elements of the scrambling sequence are used to scale the base signal in different time periods. The signal in each time period is obtained by scaling a base signal. The scrambling sequence is preferably a pseudo-random sequence. The step of scaling all samples in said signal in a time period consists of multiplying all samples of said signal with an element of said scrambling sequence.

Abstract: According to various illustrative embodiments of the present invention, a device for an integrated circuit includes a monolithic frame having a plurality of alignment features disposed thereon, the monolithic frame having a mounting surface disposed thereon for the integrated circuit, the monolithic frame also having a thermal interface area disposed thereon for the integrated circuit. The device also includes an electrical interface capable of providing an electrical connection for the integrated circuit, the plurality of alignment features being substantially independent of the electrical interface, and an adhesive layer disposed between the monolithic frame and the electrical interface.

Abstract: A system and method of aligning a micromirror array to the micromirror package and the micromirror package to a display system. One embodiment provides a method of forming and utilizing a package that exposes regions of an alignment reference plane. The device within the package is mounted on the reference plane such that the exposed regions allow precise alignment with the device in a direction perpendicular to the reference plane. Alignment surfaces formed in a display system or other system contact the reference plane at the exposed regions to position the packaged device relative to other components of the system. One embodiment of the package 400 taught has laminated layers forming the package substrate 402 and providing a precision reference plane 416 relative to the position of the micromirror device 404. The package may be formed by laminating several layers of material in sheets to form several package substrates simultaneously.

Abstract: An apparatus for generating pulses includes: (a) A delay unit having an input delay locus for receiving a delay unit input signal and an output delay locus for presenting an output delay signal. The delay unit output signal is delayed by a delay interval with respect to the input delay signal. (B) A latch coupled with the delay unit to selectively keep the delay unit input signal at at least one predetermined signal level.

Abstract: A digital sigma-delta modulator requiring minimal die area and dissipating minimal power is formed with a plurality of integration stages coupled in tandem between an input node and an output node. The bit width of signals in the integration stages is progressively reduced from the first to the last integration stage without compromising modulator accuracy. A quantizer between the last integration stage and the output node provides the final reduction of signal bit width. The gain of the modulator feedforward and feedback paths are integer powers of two to further simplify the digital computation. In an exemplary implementation, three integration stages to form a third-order modulator are coupled in tandem between the input node and the output node. The gains of feedback and feedforward paths in one preferred embodiment are unity, and in some embodiments, one feedforward path has gain of 0.5.

Abstract: A custom-molded heat sink corresponds to an individual substrate and includes a heat sink lid having at least one cavity corresponding to at least one die mounted on a substrate. A conductive layer is deposited in the at least one cavity that substantially fills the space between the at least one cavity and the at least one die when the lid is coupled to the substrate.

Abstract: To apply a desired voltage at a node driving a load impedance, a voltage source providing the desired voltage is connected to the node. In addition, a current source supplying an amount of current that would be drawn by the impedance if the voltage source alone were connected across the impedance. As a result, the voltage source may be freed substantially from supplying current, which may be advantageously used in several situations. For example, the approach can be used to connect a voltage source directly to a high load without potentially requiring a buffer between the voltage source and the node. Alternatively, the approach can be used to apply the same desired voltage at each of multiple nodes connected in series using the same voltage source without being affected by the routing resistance generally present between each pair of the nodes.

Abstract: A variable DC/DC converter system is provided that includes a feedback voltage device and a compensation device. The compensation device and compensation components are integrated into a single integrated circuit. The feedback voltage device is integrated into the single integrated circuit. The values of a first resistor and a second resistor determine the output voltage of the DC/DC converter system. The first resistor and second resistor can be external to the integrated circuit and selectable to provide a desired output voltage. Alternatively, the first resistor can be integrated into the integrated circuit, while the second resistor is external to the integrated circuit and selectable to provide a desired output voltage.

Abstract: A road vehicle keyless entry system (10) having an in-vehicle communication processor (11) and a remote transponder (15) is provided. The communication processor (10) has a radio frequency receiver (12), a low frequency transmitter/receiver (13) and a controller (14) capable of encrypting and reading the signals sent and received by the low frequency transmitter/receiver (13). The transponder (15) has a radio frequency transmitter (16) that transmits a signal to the communication processor (11) upon receipt of a manual stimulus and a low frequency transmitter/receiver (17) capable of reading and responding to encrypted signals received from the communication processor (11).

Abstract: The invention relates to a circuit arrangement for testing the operation of a current monitoring circuit for a power transistor. The power transistor consists of several single transistors of the same size connected in parallel, through which a fraction of the total current supplied to the power transistor flows. A monitoring signal proportional to the current flowing through one of the single transistors, is supplied to the current monitoring circuit, which generates an alarm signal when this monitoring signal exceeds a specified threshold value. The single transistors are divided into a group containing a small number of single transistors (T.sub.1.1 -T.sub.1.9) connected in parallel and a group with a larger number of single transistors (T.sub.2.1,1 -T.sub.2.2,9) connected in parallel, which can be driven independently of each other, where the single transistor (T.sub.S) supplying the monitoring signal belongs to the smaller group.

Abstract: A video system has a controller for controlling the transfer of data from a processor to a CRT monitor. The controller has two clocks and a CRT interface for synchronously interfacing the controller to the CRT monitor, a second interface for synchronously interfacing the controller to the processor. A first clock source provides timing for the CRT interface and is in synch with the timing of the CRT monitor. A second clock source provides timing for the processor interphase which is in synch with the timing of the processor.