Abstract: An integrated electronic device includes circuitry for providing a system supply voltage from a primary power supply. The circuitry has a high power (HP) stage coupled to the primary power supply and having an output node coupled to a supply system node for providing a HP system supply voltage level and a HP output current such that the HP stage is configured to be active in a full power mode, and a low power (LP) stage coupled to the primary power supply and to the supply system node through a voltage follower for providing a LP supply voltage level and an LP output current such that the LP stage is configured to be active in a low power mode.

Abstract: Various apparatuses, methods and systems for boosting an amplifier slew rate are disclosed herein. For example, some embodiments of the present invention provide an apparatus including a pair of inputs connected to a pair of differential input devices in an amplifier, a current source, a first current path connected to the current source, a second current path connected to the current source and to the pair of differential input devices, a switch in the first current path, and a voltage difference signal connected between the pair of inputs and the switch. The voltage difference signal represents the voltage difference between the pair of inputs. The conductance of the switch is inversely proportional to the voltage difference signal.

Abstract: A converter has a main feedback path and two auxiliary feedback paths from an output node to an auxiliary differential input pair of a comparator. The auxiliary feedback paths have different RC time constants so that a differential ramp signal is effectively applied to the auxiliary differential inputs of the comparator. The circuit design compensates for a negligibly small equivalent series resistor of an output capacitor so that modern capacitors may be used without compromising the stable oscillation of the converter.

Abstract: The invention relates to an electronic device that includes a plurality of buffers and a phase locked loop. For each buffer a fractional divider is provided which is coupled to receive the output from the phase locked loop and configured to feed a divided output signal to a respective buffer. A spread spectrum clock control logic stage in the spread spectrum clock (SSC) is provided which is configured to individually adjust a value of the division of each fractional divider in order to individually and independently modulate the output signal of each fractional divider according to a spread spectrum modulation scheme.

Abstract: A buffer is provided. The buffer includes a first switch and a second switch coupled in series at a first output node, a third switch and a fourth switch coupled in series at a second output node, a first current source and a second current source. The first current source is coupled with one side to the first switch and the third switch and with another side to a first supply voltage, the second current source is coupled with one side to the second switch and the fourth switch and with a second side to a second supply voltage. The first current source is configured to adjust an output swing in a first operation mode and in a second operation. The second current source is configured to adjust a common mode voltage level of the output signal in the first operation mode and to provide maximum series resistance in the second operation mode.

Abstract: An electronic device including a semiconductor die, which has a top surface that is configured to operate as a printed circuit board so as to provide connections for at least one passive component, in particular a passive surface mounted device (SMD).

Abstract: The network node includes a local crystal oscillator for providing a time reference derived from the clock signal produced by the local crystal oscillator, a reset stage for resetting the network node in response to a bus reset pulse received through the network and a control means for issuing a bus reset pulse of a predetermined length substantially greater than a clock period of the clock signal of the local crystal oscillator. Further the network node includes a bus reset detector for determining a length of the received bus reset pulse based on the local time reference. The bus reset detector in the network node is also adapted to adjust the local time reference based on the determined length of the received bus reset pulse.

Abstract: The invention relates to an electronic device which comprises a comparator coupled to monitor a first supply voltage level at a first supply voltage node. The comparator comprises a differential input transistor stage having one input coupled to the first supply voltage node and the other input coupled to receive a reference voltage level, a first current source configured to supply a current of a first magnitude, a second current source configured to supply a current of a second magnitude, and a capacitor. The first magnitude is greater than the second magnitude and the first current source is coupled with one side to the differential input stage for supplying the differential input stage and with the other side to a first node. The second current source is coupled with one side to the first node and with the other side to a second supply voltage node having a second supply voltage level and the capacitor is coupled with one side to the first node and with the other side to the first supply voltage node.

Abstract: Here, a driver for an light emitting diode (LED) is provided. Within this driver, several differential pairs of bipolar transistors are employed in an input stage and output stage along with a control loop. Collectively, these components operate together to drive the LED with a low headroom voltage while still achieving high driver performance in terms of edge speed and jitter.

Abstract: A coupling line is provided for coupling a signal generator to a device under test and includes a first Zener diode and a second Zener diode. The first Zener diode and the second Zener diode are coupled in an antiserial manner. They are adapted to couple the signal generator to the device under test when the signal generator is active and decouple the signal generator from the device under test when the signal generator is inactive.

Abstract: An integrated regulated current drive circuit for driving a squib of an inflatable airbag has a current sense resistor connected in series with a load, and a reference resistor connected in series with a reference current source. Both resistors are matched to define a precise ratio of resistance values which determines the amount of current fed to the squib. Both resistors are implemented by combining a number of identical on-chip resistor elements.

Abstract: A method of manufacturing a semiconductor device, the method comprising: taking an SOI substrate comprising a bulk substrate, a buried insulating layer and an active layer, and implanting the bulk substrate from the side of and through the insulating layer and the active layer so as to generate an area having an increased doping concentration in the bulk substrate at the interface between the bulk substrate and the insulating layer.

Abstract: A method of forming an integrated deep and shallow trench isolation structure comprises depositing a hard mask on a film stack having a plurality of layers formed on a substrate such that the hard mask is deposited on a furthermost layer from the substrate, imprinting a first pattern into the hard mask to define an open end of a first trench, imprinting a second pattern into the hard mask to define an open end of a second trench, and etching into the film stack the first trench to a first depth and the second trench to a second depth such that the first trench and the second trench each define a blind aperture in the surface of the film stack.

Abstract: An electronic device for switched DC-DC conversion of an input voltage level into an output voltage level, comprising a first power switch and a second power switch, being connected in parallel and having a different gate width, and a driving stage that is configured to selectively drive the first power switch and/or second power switch depending on a load current output.

Abstract: An apparatus is provided that uses a first level shifter for performing a voltage shift of a low level input signal of a first voltage domain to a high level output signal of a second voltage domain. The first level shifter comprises a storing element in the second voltage domain, an input stage coupled to the storing element for providing a signal state to be stored in the storing element and a feedback loop from an output of the storing element to the input stage for controlling the input stage in response to a transition of a high level output signal of the storing element.

Abstract: The invention relates to a DC-DC converter, which includes a power stage driven by a pulse width modulator, a first error amplifier with a first input coupled to a first reference voltage source and a second input coupled to a current sink through which a current is fed from an output of the power stage to receive a first feedback voltage (FB1), a second error amplifier with a first input coupled to a second reference voltage source and a second input coupled to the output of the power stage to receive a second reference voltage (FB2), and switching means (SW1) for connecting a control input of the pulse width modulator with the output of the first error amplifier in a current regulation mode and with the output of the second error amplifier in a voltage regulation control mode.

Abstract: An electronic device includes circuitry for driving a light-emitting diode (LED) or other light-emitting semiconductor device.

Abstract: A DC-DC converter has a control circuit for controlling a high-side power transistor and a low-side power transistor connected in series between supply terminals to which an input supply voltage is applied. The converter has a switching node at the interconnection of the power transistors for connection of an inductor to which a load is connected. The control circuit has a feedback loop that provides a pulse width modulated control signal, logic circuitry to which the pulse width modulated control signal is applied and gate drivers with inputs connected to outputs of the logic circuitry and outputs applying gate drive signals to the gates of the power transistors. A digital signal is obtained which is indicative of whether the converter switching node is at a potential above or below a zero reference at the time of the turn-off edge of the low-side gate drive signal.

Abstract: A buffer is provided. The buffer includes a buffering stage that receives an enable signal and an input signal and that provides an output signal and a bandgap stage that is coupled to the buffering stage and that is activated and deactivated by the enable signal. In particular, the buffering stage includes a buffering substage that includes a buffering transistor that is coupled to the input stage, wherein the buffering transistor is formed on a substrate, and wherein the buffering transistor has a channel with a doping concentration that is approximately the same as the substrate.

Abstract: An electronic device is provided for controlling a current. The electronic device includes a first MOS transistor coupled with a gate to a common gate node, with a source to ground and with a drain to a pin so as to receive from the pin a current to be controlled. There is a second MOS transistor coupled with a gate to the common gate node, with a source to ground and with a drain so as to receive a reference current controlled by a control loop. There is a first resistor coupled between the common gate node and ground.