Abstract: Implementing a piecewise-polynomial-continuous function in a translinear circuit generally involves translinear elements that form translinear loops that are linked by a clamp transistor. A first translinear loop controls a first portion of the piecewise-polynomial-continuous function in a first area of operation. A second translinear loop controls a second portion of the piecewise-polynomial-continuous function in a second area of operation. When activated in the second area of operation, the clamp transistor draws current through one of the translinear elements without drawing current away from another translinear element of the translinear circuit.

Abstract: A powered device receives electrical power through a data transmission cable from a power supplying device that monitors a load on the data transmission cable and turns off the power to the load if the load is outside of a range. The powered device draws a first current at least part of a time during which the powered device is in a low power mode. The powered device is operable during the low power mode to draw a second current. And the powered device increases and decreases the second current to maintain a sum of the first current and the second current, or a level of a current into the powered device, at least at a minimum level for at least a portion of a cycle time.

Abstract: The memory control this invention includes a microprogram-read-only-memory (CROM) containing micro-instructions for operation of an integrated-circuit memory, a program counter multiplexer (PCM) to select instructions from the control-read-only-memory, a micro-instruction decoder with BILBO control (MID/BC), a test input multiplexer (TIM) to test control signals, an optional status output register (SOR) to generate control signals, and a subroutine stack (SS) to allow function calls. A program counter (PC) takes an index signal from the micro-instruction decoder with BILBO control (MID/BC) and a signal from the program counter multiplexer (PCM), and from those signal, generates a next microcode address. Complex program, erase, and compaction instructions for the integrated-circuit memory are implemented using a relatively small number of control-read-only-memory locations and using a relatively small surface area on the memory chip.

Abstract: An array source signal discharge controller device (10) includes a pulse converter circuit (12) that receives an erase pulse signal (ERPULSE). The pulse converter circuit (12) converts the erase pulse signal (ERPULSE) into a pulse control signal (ERPCL) that is subsequently translated into a higher voltage level bias signal (ECL.sub.--). The higher voltage level bias signal (ECL.sub.--) drives array source signal generator circuits (16) that produce array source signals (AS) to erase particular array subsections of memory as determined by a selection circuit (17). The array source signal generator circuits (16) also generate array source command signals (ASCOM.sub.--) to indicate a discharging status of all array source signals (AS). An erase completion detector circuit (18) monitors the array source command signals (ASCOM.sub.--) and generates an array source detect signal (ASDET) to indicate completion of array source signal (AS) discharging.