Abstract: Described herein is a technology for account for messages or data that are not read by a receiver unit in a device. A sender unit collects data from a data source, which is passed on stored in an inter-processor communication (IPC) module. The receiver unit receives the data from the IPC module, while the sender unit predicts an expected time that that receiver unit will read the data and whether the receiver unit will actually read the data.

Abstract: In an integrated circuit, a metal-insulator-metal (MIM) diode includes: a first metallization structure level having a first metal layer; a first dielectric layer over the first metal layer; a metal contact or via on the first metal layer and extending through a portion of the first dielectric layer; and a second metallization structure level having a second metal layer; and a second dielectric layer over the second metal layer. The diode has a first electrode on the metal contact or via, a multilayer dielectric structure on the first electrode, and a second electrode between the multilayer dielectric structure and the second metal layer.

Abstract: This invention is an improvement of a Hierarchical Do-Dag based RPL (H-DOC) network configuration where the network address of each node corresponds to its location within the hierarchical network. Network addresses are initialized hierarchically. Candidate patent nodes signal availability. Candidate child nodes respond to a selected candidate parent node with a temporary address. The selected candidate parent node acknowledges selection and communicates a hierarchical address for the child node in a transmission to the temporary address. The child node changes its address to the hierarchical address from the parent node. When a node switches parent nodes, it signals the old parent node to deallocate it as a child node, and then signals a selected candidate parent node with a temporary address.

Abstract: Embodiments of methods and systems for supporting coexistence of multiple technologies in a Power Line Communication (PLC) network are disclosed. A long coexistence preamble sequence may be transmitted by a device that has been forced to back off the PLC channel multiple times. The long coexistence sequence provides a way for the device to request channel access from devices on the channel using other technology. The device may transmit a data packet after transmitting the long coexistence preamble sequence. A network duty cycle time may also be defined as a maximum allowed duration for nodes of the same network to access the channel. When the network duty cycle time occurs, all nodes will back off the channel for a duty cycle extended inter frame space before transmitting again. The long coexistence preamble sequence and the network duty cycle time may be used together.

Abstract: An integrated circuit chip includes an interleaved analog-to-digital converter (ADC) and an interleaving calibration circuit. The interleaved ADC includes a plurality of ADCs that are each configured to sample an analog signal. The interleaved ADC is configured to convert the analog signal into an interleaved analog-to-digital signal (IADC signal) that includes a plurality of spurious signals formed from mismatches between the plurality of ADCs. The interleaving calibration circuit is configured to receive the IADC signal from the interleaved ADC, generate a mismatch profile estimate corresponding to the plurality of spurious signals to generate one or more mismatch profile estimates, determine whether a first mismatch profile estimate is in a frequency band of interest, and, in response to a determination that the first mismatch profile estimate is in the frequency band of interest, generate a set of model parameters based on the first mismatch profile estimate.

Abstract: An integrated circuit containing metal replacement gates may be formed by forming a nitrogen-rich titanium-based barrier between a high-k gate dielectric layer and a metal work function layer of a PMOS transistor. The nitrogen-rich titanium-based barrier is less than 1 nanometer thick and has an atomic ratio of titanium to nitrogen of less than 43:57. The nitrogen-rich titanium-based barrier may be formed by forming a titanium based layer over the gate dielectric layer and subsequently adding nitrogen to the titanium based layer. The metal work function layer is formed over the nitrogen-rich titanium-based barrier.

Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.

Abstract: A system and method are disclosed for providing electrically isolated communications between two USB2 devices. Two isolating eUSB2 repeaters are utilized to implement a digital isolation barrier between the two USB2 devices. The isolating eUSB2 repeaters are configured to broker isolated communications between the two USB2 devices using a modified eUSB2 protocol that allows the two isolating eUSB2 repeaters to interoperate across the isolating barrier. The modified eUSB2 protocol allows the two isolating eUSB2 repeaters to broker isolating communications on behalf of the USB2 devices without the use of an accurate clock signal. The modified eUSB2 protocol utilized by the isolating eUSB2 repeaters is configured in particular to support certain end-of-packet translations between USB2 data and the modified eUSB2 protocol, management of certain USB2 bus state transitions and assignment of roles to the two isolating eUSB2 repeaters.

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract: A wireless receiver (74) for receiving signals from a transmitter (72). The transmitter comprises a plurality of transmit antennas (TAT1?, TAT2?) for transmitting the signals, which comprise respective independent streams of symbols. Additionally, interference occurs between the respective streams. The receiver comprises a plurality of receive antennas (RAT1?, RAT2?) for receiving the signals as influenced by a channel effect between the receiver and the transmitter. The receiver also comprises circuitry (80) for multiplying the signals times a conjugate transpose of an estimate of the channel effect and times a conjugate transpose of a linear basis transformation matrix. The receiver also comprises circuitry (84) for selecting the linear basis transformation matrix from a finite set of linear basis transformation matrices. Lastly, the receiver comprises circuitry (88) for removing the interference between the respective streams.

Abstract: A circuit includes an amplifier output stage that includes a high switch and a low switch that generates a pulse width modulated (PWM) output signal to provide a load current to a load in response to a PWM input signal. The circuit includes a high gate drive that drives the high switch with a PWM high drive signal derived from the PWM input signal. This includes a low gate drive that drives the low switch with a PWM low drive signal derived from the PWM input signal. The circuit includes an edge corrector that adjusts at least one of a leading edge and a trailing edge of the PWM input signal to compensate for response time differences with respect to a direction of the load current to the load.

Abstract: A method of forming packaged semiconductor devices includes providing a lead frame sheet of flat no-lead lead frames having a semiconductor die on a die pad, terminals, and plastic encapsulation except on a back side of the sheet to provide an exposed thermal die pad and exposed back sides of the terminals. Partial sawing in saw lanes begins from the back side through the terminals terminating within the plastic encapsulation to provide exposed side walls of the terminals and of the plastic encapsulation. The exposed thermal pad and exposed back side of the terminals are all shorted together to form exposed electrically interconnected metal surfaces (interconnected surfaces). The interconnected surfaces are electroplated with a solder wetable metal or metal alloy plating layer. The interconnected surfaces are decoupled. A second sawing in the saw lanes finishes sawing through the plastic encapsulation to provide singulation, forming a plurality of packaged semiconductor devices.

Abstract: In response to a signal failing to exceed an estimated level of noise by more than a predetermined amount for more than a predetermined continuous duration, the estimated level of noise is adjusted according to a first time constant in response to the signal rising and a second time constant in response to the signal falling, so that the estimated level of noise falls more quickly than it rises. In response to the signal exceeding the estimated level of noise by more than the predetermined amount for more than the predetermined continuous duration, a speed of adjusting the estimated level of noise is accelerated.

Abstract: An integrated circuit (“IC”) assembly includes an IC die with a metallization layer on a top surface thereof. A plurality of lead wires are bonded at first end portions thereof to the metallization layer. A conductive layer is attached to the metallization layer and covers the first ends of the lead wires.

Abstract: An energy harvesting system for transferring energy from an energy harvester (2) having an output impedance (Zi) to a DC-DC converter (10) includes a maximum power point tracking (MPPT) circuit (12) including a replica impedance (ZR) which is a multiple (N) of the output impedance. The MPPT circuit applies a voltage across the replica impedance that is equal to an output voltage (Vin) of the harvester to generate a feedback current (IZR) which is equal to an input current (Iin) received from the harvester, divided by the multiple (N), to provide maximum power point tracking between the harvester and the converter.

Abstract: Traditionally, mixers have been arranged symmetrically around the input signal, which has resulted in problems due to self-mixing or feed-through by the local oscillator signal. Here, however, the arrangement for a mixer has been changed to generally avoid self-mixing of the local oscillator signal. In particular, transistors in the switching core are merged according to the portion of the local oscillator signal received. This, in turn, results in the conductors, which carry the different portions of the local oscillator signal, being separated (or not having any crossings) so as to generally eliminate self-mixing or feed-through of the local oscillator signal. Complex IQ mixers realized using this arrangement benefit from improved sideband suppression and image rejection.

Abstract: A semiconductor device includes a leadframe, a semiconductor chip, a packaging compound. The leadframe has a pad with straps. Leads on the leadframe include first and second portions. The pad, the straps, and the leads have a mechanically rough surface. The semiconductor chip is attached to the pad and wire bonded to the first lead portions. A packaging compound encapsulates the chip, the pad, the straps, the bonding wires and the first lead portions. The second lead portions are left un-encapsulated. The strap ends are exposed on the surface of the package. At least one of the straps includes a portion adjacent to the exposed end. This portion having a mechanically smooth surface transitioning by a step into the rough surface of the remainder of the strap.

Abstract: Systems and methods for implementing symbol-level repetition coding in power line communications (PLC) are described. In some embodiments, these systems and methods may provide reliable communication in severe channel environments of PLC networks, at least in part, by changing the forward error correction (FEC) used by various devices operating within current PLC systems. For example, a method may include receiving a PLC signal and applying convolutional encoding to the received signal, the convolutional encoding producing an encoded signal. The method may also include performing a subcarrier modulation operation upon the encoded signal, the subcarrier modulation operation producing a modulated signal. The method may further include applying symbol-level repetition coding to the modulated signal, the symbol-level repetition coding producing a repetitious signal. In some cases, one or more distinct repetition patterns may be applied to different symbols or portions thereof.

Abstract: An electrostatic discharge (ESD) device for protecting an input/output terminal of a circuit, the device comprising a first transistor with an integrated silicon-controlled rectifier (SCR) coupled between the input/output (I/O) terminal of the circuit and a node and a second transistor with an integrated silicon-controlled rectifier coupled between the node and a negative terminal of a supply voltage, wherein the silicon-controlled rectifier of the first transistor triggers in response to a negative ESD voltage and the silicon-controlled rectifier of the second transistor triggers in response to a positive ESD voltage.

Abstract: One aspect of the present invention includes a light-emitting diode (LED) power supply system. The system includes an LED regulator configured to monitor at least one LED voltage associated with a respective at least one activated LED string and to generate an LED regulation voltage based on the at least one LED voltage relative to an LED power voltage that provides power to the at least one activated LED string. The system also includes a power converter configured to generate the LED power voltage and to regulate the LED power voltage based on the LED regulation voltage.