Abstract: The present invention provides a method for patterning a metal gate electrode and a method for manufacturing an integrated circuit including the same. The method for patterning the metal gate electrode, among other steps, includes forming a metal gate electrode layer (220) over a gate dielectric layer (210) located on a substrate (110), and patterning the gate electrode layer (220) using a combination of a dry etch process (410) and a wet etch process (510).

Abstract: Fabricating a semiconductor includes forming a conductive layer outwardly from a surface of a substrate. A mask layer comprising a hard mask is deposited outwardly from the conductive layer to pattern the conductive layer to form a gate stack. The conductive layer is etched to remove the conductive layer from the surface of the substrate and to form the gate stack, where the mask layer is disposed outwardly from the gate stack. Ions are implanted outwardly from the surface of the substrate, where the mask layer prevents at least a portion of the ions from penetrating the gate stack while penetrating the substrate.

Abstract: A method for making semiconductor devices such as dynamic read/write memory cell arrays of the one-transistor N- channel silicon gate type employs an ion implant of high dosage to produce N+ source/drain regions. The transistor and capacitor gates are in place when this implant is performed, and the chain oxide beneath the gates can break down due to static charge produced on the slice surface as a result of the ion implant. To prevent build-up of static charge on the surface, a thin coating of polysilicon is applied before the implant and grounded. This coating is subsequently removed by thermal oxidation or etching. Alternatively, a thermal oxide coating may be used as it will prevent the implanted arsenic from reaching the polysilicon gates, although it will penetrate a thinner thermal oxide coating over the source/drain area. Other dielectric films such as silicon nitride may also be used.