Patents Assigned to Texas Instruments Japan
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Publication number: 20090295973Abstract: This invention is a solid-state image pickup device that solves the problem of limited dynamic range in the high luminance region in an image sensor having white pixels. White pixels or yellow pixels and at least red pixels, green pixels or blue pixels are arranged in array form on the light receiving surface of a semiconductor substrate. White pixels or yellow pixels have an additional capacitance CS connected to the photodiode via the floating diffusion, a capacitance coupling transistor S that can couple or separate the floating diffusion and the additional capacitance. The proportion of white or yellow pixels to the total number of pixels is higher in a central portion of the light receiving surface than a peripheral portion. The white or yellow pixel may share a floating diffusion with a red, green or blue pixel.Type: ApplicationFiled: May 20, 2009Publication date: December 3, 2009Applicant: Texas Instruments Japan, Ltd.Inventors: Hiromich Oshikubo, Satoru Adachi, Koichi Mizobuchi
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Patent number: 7157363Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.Type: GrantFiled: September 27, 2004Date of Patent: January 2, 2007Assignees: Fujikura Ltd., Texas Instruments Japan LimitedInventors: Takanao Suzuki, Masatoshi Inaba, Tadanori Ominato, Masahiro Kaizu, Akihito Kurosaka, Masatoshi Inaba, Nobuyuki Sadakata, Mutsumi Masumoto, Kenji Masumoto
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Patent number: 7023088Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.Type: GrantFiled: May 21, 2003Date of Patent: April 4, 2006Assignees: Fujikura Ltd., Texas Instruments Japan LimitedInventors: Takanao Suzuki, Masatoshi Inaba, Tadanori Ominato, Masahiro Kaizu, Akihito Kurosaka, Masatoshi Inaba, Nobuyuki Sadakata, Mutsumi Masumoto, Kenji Masumoto
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Publication number: 20050037539Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.Type: ApplicationFiled: September 27, 2004Publication date: February 17, 2005Applicants: FUJIKURA LTD., TEXAS INSTRUMENTS JAPAN LIMITEDInventors: Takanao Suzuki, Masatoshi Inaba, Tadanori Ominato, Masahiro Kaizu, Akihito Kurosaka, Masatoshi Inaba, Nobuyuki Sadakata, Mutsumi Masumoto, Kenji Masumoto
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Patent number: 6835595Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.Type: GrantFiled: June 4, 2001Date of Patent: December 28, 2004Assignees: Fujikura Ltd., Texas Instruments Japan LimitedInventors: Takanao Suzuki, Masatoshi Inaba, Tadanori Ominato, Masahiro Kaizu, Akihito Kurosaka, Masatoshi Inaba, Nobuyuki Sadakata, Mutsumi Masumoto, Kenji Masumoto
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Publication number: 20030207494Abstract: An insulating layer (3) having an opening portion (3a) at a position conformable to an electrode pad (2) is formed. Next, a resin projection portion (4) is formed on the insulating layer (3). Thereafter, a resist film is formed which has opening portions made in regions conformable to the opening portion (3a), the resin projection portion (4) and the region sandwiched therebetween. A Cu plating layer (6) is formed by electrolytic copper plating, using the resist film as a mask.Type: ApplicationFiled: May 21, 2003Publication date: November 6, 2003Applicants: FUJIKURA LTD., TEXAS INSTRUMENTS JAPAN LIMITEDInventors: Takanao Suzuki, Masatoshi Inaba, Tadanori Ominato, Masahiro Kaizu, Akihito Kurosaka, Masatoshi Inaba, Nobuyuki Sadakata, Mutsumi Masumoto, Kenji Masumoto
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Patent number: 6469570Abstract: A voltage supply circuit capable of starting up a system while maintaining symmetry of a high level selection signal VH and a low level selection signal VL, not requiring a multistage charge pump circuit, and capable of reducing the number of parts of the system, wherein generation circuits of VD and VH are comprised of chopper type booster type switching regulators, and switching timings of a VH generation circuit 12 and a VL generation circuit 13 are controlled so that a virtual reference voltage VS (VD/2) and a middle point potential between VH and VL become the same.Type: GrantFiled: July 12, 2001Date of Patent: October 22, 2002Assignees: Texas Instruments Japan Limited, Seiko Epson CorporationInventors: Hiroyasu Inomata, Satoshi Yatabe
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Patent number: 6007920Abstract: The wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.Type: GrantFiled: June 17, 1998Date of Patent: December 28, 1999Assignees: Texas Instruments Japan, Ltd., Lintec CorporationInventors: Norito Umehara, Masazumi Amagai, Mamoru Kobayashi, Kazuyoshi Ebe
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Patent number: 5985677Abstract: A semiconductor memory chip has fuses and a redundancy memory cell which can replace a normal memory cell that is found defective by cutting off the fuses. If the normal memory cell is defective, the fuses are cut off thereby to connect the redundancy memory cell instead of the normal memory cell which is defective. The entire surface of the semiconductor memory chip is coated with a resist layer. The coated the resist layer is exposed at regions of the fuses to an energy beam, and then developed form a resist pattern. The semiconductor memory chip is etched at the regions using the resist pattern as a mask for thereby cutting off the fuses. The fuses may be spaced at intervals of 2 .mu.m or smaller, and can be cut off without causing damage to a layer beneath the fuses.Type: GrantFiled: May 21, 1997Date of Patent: November 16, 1999Assignees: Advantest Corporation, Texas Instruments JapanInventors: Naoki Nishio, Hideyuki Fukuhara, Yoichi Miyai, Yoshinobu Kagawa
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Patent number: 5943437Abstract: A surface image of a semiconductor wafer having a defect is picked up as a inspection image while a surface image of a semiconductor wafer having no defect is stored in an image memory as a reference image. A density difference image between the inspection image and the reference image. By extracting the defect in wiring and non-wiring regions from the density difference image, extract images are obtained. Two luminance information for wiring and non-wiring regions are obtained from extract images. Based on the luminance information, the type of the defect is determined and a production process where the defect has occurred is detect.Type: GrantFiled: October 7, 1996Date of Patent: August 24, 1999Assignees: Kabushiki Kaisha Kobe Seiko Sho, Texas Instruments Japan Limited, KTI Semiconductor Ltd.Inventors: Shingo Sumie, Tsutomu Morimoto, Yuichiro Gotoh, Eiji Takahashi, Shouji Kanbe, Akira Okamoto
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Patent number: 5914859Abstract: An electronic component mounting base board comprises an insulating substrate provided with a mounting portion for mounting an electronic component and a heat-sink plate disposed on an lower surface of the insulating substrate, in which the insulating substrate is provided with a wiring pattern for signal or power, a grounding pattern and a grounding hole, and the grounding hole is provided on its inner wall with a metal plated film for electrically connecting to the grounding pattern and a solder is filled in an inside of the grounding hole for electrically connecting to the heat-sink plate.Type: GrantFiled: April 22, 1997Date of Patent: June 22, 1999Assignees: Ibiden Co., Ltd., Texas Instruments Japan, Ltd.Inventors: Masaru Takada, Kiyotaka Tsukada, Morio Nakao
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Patent number: 5909415Abstract: A positioning control system for performing recording/reproducing operations by irradiating an optical beam to a predetermined position on an optical recording medium, e.g., magneto-optical disk. The control system includes a photo-detector constituted by at least two-divisional units, and a servo-error signal generating circuit which can generate at least one servo-error signal in accordance with a difference between the detection currents. Preferably, the servo-error signal generating circuit includes at least one division circuit that has two pairs of transistors, two emitters in each pair of transistors being connected together into a common emitter, bias voltages of a direct current type being applied to the respective bases of transistors on one side, and the respective collectors of the transistors on one side being connected to a common connecting portion via resistors.Type: GrantFiled: October 8, 1997Date of Patent: June 1, 1999Assignee: Fujitsu Limited & Texas Instruments JapanInventors: Akira Minami, Shigeyoshi Tanaka, Michio Matsuura, Hiromichi Kuwano, Kazuyuki Tamanoi
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Patent number: 5882956Abstract: A process for manufacturing a wafer dicing/bonding sheet of the present invention comprises a soft film, a pressure sensitive adhesive layer formed on the soft film, a processing film for polyimide type resin composed of a heat resistant resin which has been formed on the pressure sensitive adhesive layer and a polyimide adhesive layer formed on the processing film. It is preferred that the processing film be a polyethylene naphthalate film whose surface has been subjected to an alkyd release treatment. The present invention facilitates expansion to be conducted after the wafer dicing.Type: GrantFiled: January 21, 1997Date of Patent: March 16, 1999Assignees: Texas Instruments Japan Ltd., Lintec CorporationInventors: Norito Umehara, Masazumi Amagai, Mamoru Kobayashi, Kazuyoshi Ebe
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Patent number: 5875124Abstract: A full adder that operates rapidly with low power supply voltage and minimal power consumption, and further, that occupies a small area on a semiconductor element. A sum signal calculation circuit 10 of full adder 1 performs addition of input signals A and B and carry in signal C and outputs sum signal S.sub.out. Carry signal calculation circuit 16 outputs carry out signal C.sub.out corresponding to the combination of the logic values of input signals A and B and carry in signal C. Sum signal calculation circuit (10) is composed of addition signal generation circuit (12) and sum signal generation circuit (14). Addition signal generation circuit 12 performs XOR logic operations on input signals A and B. Sum signal generation circuit 14 outputs the results of full addition operations on inputs signals A and B and carry in signal C as sum signal S.sub.out, based on the results of XOR logic operations by addition signal generation circuit (12) and carry in signal C.Type: GrantFiled: October 16, 1997Date of Patent: February 23, 1999Assignee: Texas Instruments Japan Ltd.Inventor: Hiroshi Takahashi
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Patent number: 5650801Abstract: A drive circuit in which the rise and fall characteristics with multiple voltages are made the same, while maintaining a high breakdown voltage. Drive circuit 70, which supplies power supply voltages VH and VL and voltage VM intermediate between them to output pad 32, is composed of p-channel MOS transistor P5 and n-channel MOS transistors N5, N6 and N7. When the output voltage changes from VH to VM, both transistors N6 and N7 conduct, and when the output voltage changes from VL to VM, only transistor N6 conducts. The transistors that supply intermediate voltage VM are constructed of transistors of the same conductivity type, so that the rise and fall characteristics to VM can be made the same while the breakdown voltage of the transistors in the circuit that supplies this intermediate voltage VM is kept high.Type: GrantFiled: June 7, 1995Date of Patent: July 22, 1997Assignee: Texas Instruments Japan, Ltd.Inventor: Masahiko Higashi
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Patent number: 5636191Abstract: A positioning control system for performing recording/reproducing operations by irradiating an optical beam to predertermined position on an optically recording medium, e.g., magneto-optical disk, includes a photo-detector constituted by at least two-divisional units; and a servo-error signal generating circuit which can generate at least one servo-error signal in accordance with a difference between the detection currents.Type: GrantFiled: April 13, 1995Date of Patent: June 3, 1997Assignees: Fujitsu Limited, Texas Instruments Japan LimitedInventors: Akira Minami, Shigeyoshi Tanaka, Michio Matsuura, Hiromichi Kuwano, Kazuyuki Tamanoi
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Patent number: 5349218Abstract: A semiconductor integrated circuit device has a semiconductor memory cell array including word lines, data lines and a plurality of memory cells provided at cross points of the word and data lines. Each memory cell has a cell selection transistor and an information storage capacitor connected in series. The cell selection transistor in one cell includes first and second doped regions formed in a main surface of a semiconductor substrate, a first insulating film formed on the main surface between the first and second doped regions and a control electrode layer formed on the first insulating film between the first and second doped regions. The first doped region is connected with a data line, while the control electrode is connected with a word line.Type: GrantFiled: April 29, 1992Date of Patent: September 20, 1994Assignees: Hitachi, Ltd., Texas Instruments Japan, Inc.Inventors: Yoshitaka Tadaki, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Toru Kaga, Jun Murata, Osaomi Enomoto
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Patent number: 5297530Abstract: A heating device for injected fuel in an internal combustion engine is disposed at an upper wall of an intake port. The heating device includes a casing and a plurality of fins integrally connected to a lower plate of the casing. A heater is disposed between the intake port and the casing. The fins are arranged to downwardly extend from said supporting member and along the injected direction of the injected fuel. Therefore, the atomization of the injected fuel is accelerated by the heating of the heating device.Type: GrantFiled: September 11, 1992Date of Patent: March 29, 1994Assignees: Nissan Motor Co., Ltd., Texas Instruments Japan LimitedInventors: Noboru Kaneko, Takahisa Yamashita
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Patent number: 5199071Abstract: A method and apparatus for matching operation modes of modems for connection of terminals to a telephone line, i.e., matching operation forms determined by a communication speed, a coding format, a synchronizing format, etc., on both the calling and answering sides of the telephone line. When the answering side detects an extension specifying signal sent from the calling side, an operation mode of a modem corresponding to the extension specifying signal is used to select the specified operation mode from among a plurality of operation modes for modem circuits equipped on the answering side, for matching the operation mode of the answering side modem with that on the calling side. The answering side modem has a function of detecting a push-button dial signal serving as the extension specifying signal, and a function of providing the plurality of operation modes for the modem and optionally changing the operation mode upon an instruction from an answering side terminal.Type: GrantFiled: July 10, 1990Date of Patent: March 30, 1993Assignees: NTT Data Communications Systems Corporation, Ohkura Electric Co., Ltd., Texas Instruments Japan Ltd.Inventors: Kenichi Abe, Masumi Kaneuchi, Kenji Kurashina, Kenzou Kaji, Kikuo Sumiyoshi
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Patent number: 5153897Abstract: The operation modes of a plurality of modems in a communication system are matched with each other for connection of digital terminals to an analog telephone line on both the calling and answering sides of the analog telephone line. For example, operation modes of modems on both sides of the analog telephone line can automatically be matched with each other by transferring a mode instructing signal with DTMF, using multi-frequency DTMF symbols for a select signal employed in the telephone line, between digital terminals connected to both ends of the telephone line.Type: GrantFiled: July 10, 1990Date of Patent: October 6, 1992Assignees: Texas Instruments Japan Ltd., NTT Data Communications Systems Corporation, Ohkura Electric Co., Ltd.Inventors: Kikuo Sumiyoshi, Kenichi Abe, Masumi Kaneuchi, Kenji Kurashina, Kenzou Kaji