Patents Assigned to Texas Instruments Lehigh Valley Incorporated
  • Publication number: 20110198927
    Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.
    Type: Application
    Filed: April 26, 2011
    Publication date: August 18, 2011
    Applicant: Texas Instruments Lehigh Valley Incorporated
    Inventors: Jacek Korec, Stephen L. Colino
  • Patent number: 7952145
    Abstract: A semiconductor device includes a semiconductor substrate, a first p-channel laterally diffused metal oxide semiconductor (LDMOS) transistor formed over the semiconductor substrate and additional p-channel LDMOS transistors formed over the semiconductor substrate. First drain and gate electrodes are formed over the substrate and are coupled to the first LDMOS transistor. Additional drain and gate electrodes are formed over the substrate and are coupled to the second LDMOS transistor. A common source electrode for the first and second LDMOS transistors is also formed over the substrate.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: May 31, 2011
    Assignee: Texas Instruments Lehigh Valley Incorporated
    Inventors: Jacek Korec, Stephen L. Colino
  • Patent number: 7589378
    Abstract: A laterally diffused metal-oxide-semiconductor transistor device includes a substrate having a first conductivity type with a semiconductor layer formed over the substrate. A source region and a drain extension region of the first conductivity type are formed in the semiconductor layer. A body region of a second conductivity type is formed in the semiconductor layer. A conductive gate is formed over a gate dielectric layer that is formed over a channel region. A drain contact electrically connects the drain extension region to the substrate and is laterally spaced from the channel region. The drain contact includes a highly-doped drain contact region formed between the substrate and the drain extension region in the semiconductor layer, wherein a topmost portion of the highly-doped drain contact region is spaced from the upper surface of the semiconductor layer. A source contact electrically connects the source region to the body region.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: September 15, 2009
    Assignee: Texas Instruments Lehigh Valley Incorporated
    Inventors: Christopher Boguslaw Kocon, Shuming Xu, Jacek Korec