Abstract: When there is an area (chargeable area) that may be avoided, a suitable bypass route is presented with suitable timing. When a retrieved recommended route passes through an area (for example, a chargeable area) that may be avoided, a navigation device searches in advance for a bypass route that starts from a branch point (such as an intersection) on the recommended route before the area and bypasses the area without taking a long way around the area. The navigation device presents the recommended route before the area is approached, and presents the bypass route for the first time when the branch point becomes near.

Abstract: A method and an optical system employing the same are provided for providing uniform illumination light with a desired illumination field using a surface diffuser.

Abstract: Various systems and methods for clock management. As one example, a system for clock management is disclosed that includes a controllable oscillator, an oscillation control source, and a sample and hold circuit. The sample and hold circuit is disposed between the oscillation control source and the controllable oscillator, and is operable to introduce a transfer function having a sin x/x characteristic with a null at a switch frequency applied to the sample and hold circuit.

Abstract: A low-profile, high power ball grid array, or land grid array, device including a plastic tape having first and second surfaces, a portion of the first surface covered with an adhesive layer. First and second openings are stamped through the tape and adhesive layer, the first openings configured for solder balls and the second openings configured to accommodate circuit chips. A copper foil is laminated on the adhesive layer, and the portion of this copper foil in the second openings is mechanically shaped into a position coplanar with the second surface, whereby it becomes useable as a chip mount pad, exposed after encapsulation for low resistance heat dissipation. The circuit chips are mounted by means of a thermally conductive material on each of the chip mount pads. Encapsulating material surrounds the mounted chips in low profile. For ball grid array devices, solder balls are attached to the copper foil exposed by the first openings in the tape.

Abstract: A method and system for ordering a priority for a function to receive any type of processing resources in a system that includes a plurality of functions. The invention includes identifying a plurality of instances of the functions that use processing resources. The invention then determines an importance of at least one of said instances by using fuzzy logic in a fuzzy inference system.

Abstract: Method for computing distances to received data points. A preferred embodiment comprises determining a first point on a grid nearest to the received point, computing a second point closest to the received point inside a specified area, wherein the second point is a point in a first coset, computing a third, fourth, and fifth point, wherein each point is a member of a different coset and each point is the closest point in its coset to the received point, and computing a distance from the received point to each of the second, third, fourth, and fifth points.

Abstract: A method for improving high-? gate dielectric film (104) properties. The high-? film (104) is subjected to a two step anneal sequence. The first anneal is performed in a reducing ambient (106) with low partial pressure of oxidizer to promote film relaxation and increase by-product diffusion and desorption. The second anneal is performed in an oxidizing ambient (108) with a low partial pressure of reducer to remove defects and impurities.

Abstract: A method and/or a system of control signal synchronization of a scannable storage circuit is disclosed. In one embodiment, a system includes a first circuit to operate based on a first voltage of a first power supply, a second circuit to operate based on a second voltage of a second power supply, a level shifter circuit between the first circuit and the second circuit to translate between the first voltage of the first power supply and the second voltage of the second power supply, and a n-channel metal-oxide semiconductor field-effect transistor (nMOSFET) having a gate input of the second voltage and serially coupled in a fall path of the level shifter circuit to increase a rate of a capacitive discharge such that the rate of a capacitive discharge charge is substantially equal to a rate of a capacitive charge (e.g., the fall delay may also increase a bit because of an extra transistor).

Abstract: A method that allows a digital communications system to detect the presence of transmitted messages in noisy environments. The system includes an OFDM transmitter and an OFDM receiver. The OFDM transmitter converts a digital signal to be transmitted to a plurality of sub-signals, each corresponding to a respective sub-carrier frequency. The signal is a packet including a preamble field having a known data pattern. The transmitter pre-codes the preamble data pattern, maps the data to corresponding phase information, converts the sub-signals to the time domain, and converts the sub-signals to analog form for subsequent transmission. The OFDM receiver receives the transmitted sub-signals, converts the sub-signals to digital form, converts the sub-signals to the frequency domain, and subjects the sub-signals to preamble detection processing to detect the signals' presence.

Abstract: A method for detecting a boundary between two sequences in a wireless local area network is presented that permits rapid detection of the boundary. The method includes provisions for proper operation when significant interference and multi-path can degrade the received transmission significantly. Additionally, when a modification is made to the signaling format to signal a special enhanced mode with performance and features above those that are specified in a single technical standard, the method detects the boundary between sequences regardless of whether they have the standard format or the modified format.

Abstract: Testing the components of I/O paths in an integrated circuit at-speed operation (i.e., the speed at which the integrated circuit would be operated during normal non-test mode). In an embodiment, boundary scan cells of different paths are connected in a scan chain, and each scan cell tests the corresponding component (e.g., buffer) by launching data at a first time instance and receiving the result of the data at a second time instance, with the duration between the first time instance and the second time instance corresponding to the at-speed operation. If the data is received accurately, the component may be deemed to be operating accurately at-speed.

Abstract: System and method for a burst-mode switching voltage regulator with good stability and small output voltage ripple. A preferred embodiment comprises a current sense circuit coupled to a power switch in the burst-mode switching voltage regulator to sense a current flowing through the power switch. The sensed current can then be used (in conjunction with a feedback control signal that is based on the output voltage and is generated at the output of the burst-mode switching generator) to control the operation of the power switch to regulate the output voltage of the burst-mode switching voltage regulator. This enables the use of an output regulator with a small equivalent series resistance to minimize voltage ripple while providing good operational stability and fast transient response.

Abstract: A translinear network (34) has first (Q1, Q2, Q3, Q4) and second (Q4, Q3, Q5, Q6) translinear loops. A Trafton-Hastings clamp circuit (36) is connected to generate a piecewise-polynomial-continuous current IY, the value of which becomes undefined when current IX=0 due to a removable singularity in the transfer equation at this point. A current mirror (38) comprising a plurality of transistors (M1, M2, M3) is coupled to the Trafton-Hastings clamp circuit (36), and operates to add additional currents in transistors Q3 and Q5 to IX, when the Trafton-Hastings clamp transistor (Q7) conducts, so as to perturb the removable singularity in the transfer equation into the left half-plane.

Abstract: A metal structure for an integrated circuit, which has copper interconnecting metallization (311) protected by an overcoat layer (320). A portion of the metallization is exposed in a window (301) opened through the thickness of the overcoat layer. The metal structure comprises a patterned conductive barrier layer (330) positioned on the copper metallization, wherein this barrier layer forms a trough with walls (331) conformal with the overcoat window. The height (331a) of the wall is less (between 3 and 20 %) than the overcoat thickness (320a), forming a step (340). A plug (350) of bondable metal, preferably aluminum, is positioned in the trough and has a thickness equal to the trough wall height (331a).

Abstract: The present invention facilitates semiconductor fabrication by providing methods of fabrication that selectively form high-k dielectric layers within NMOS regions. An oxide layer is formed in core and I/O regions of a semiconductor device (506). The oxide layer is removed (508) from the core region of the device. A high-k dielectric layer is formed (510) over the core and I/O regions. Then, the high-k dielectric layer is removed (512) from PMOS regions of the core and I/O regions. A silicon nitride layer is grown (516) within PMOS regions of the core and I/O regions by a low temperature thermal process. Subsequently, an oxidation process is performed (518) that oxidizes the silicon nitride into silicon oxynitride.

Abstract: A device comprises a first component operable to produce a plurality of discrete multitone symbols based in part on a subchannel spacing and a cyclic extension length and a second component operable to determine the subchannel spacing and the cyclic extension length, the cyclic extension length selected based on the subchannel spacing to increase the number of discrete multitone symbols transmitted during a low noise interval of a cyclostationary noise environment.

Abstract: Selecting one of multiple antennas to receive signals in a wireless packet network. Correlation value and gain needed to boost the signal up to a desired power (or the signal strength of the received signal) are determined for each antenna by examining the non-payload portion (e.g., preamble) of the packet. The antenna with the best SNR is then chosen based on the rule given. In an embodiment, the correlation value is determined based on the Barker Sequence employed for each bit in the preamble. The selection may be performed for each data packet, thereby using the antenna receiving the signal most conducive to recovery of the data bits (including payload) in each data packet.

Abstract: Linking addressable shadow port (LASP) and protocol allows addressing the LASP and configuring the connection of multiple Secondary Test Access Ports (TAPs) of the LASP using a single protocol or protocol bypass inputs. Multiple LASPs are cascaded and the connection of their secondary TAPs are configured using the LASP protocol or protocol bypass inputs.

Abstract: A power equalization circuit in a transformer-based device having a plurality of isolated voltage outputs is provided. The circuit comprises: a threshold detection circuit configured to receive an error signal derived from a selected voltage at one of the isolated voltage outputs, and to determine whether the selected voltage is above a voltage threshold based on the error signal; a timer circuit configured to activate a wait signal after a maximum voltage drift time has expired since the selected voltage rose above the voltage threshold, and to activate a wink signal coincident with the wait signal; an overdrive current source configured to drive an error current to an overdriven value in response to the wait signal; and a commutator circuit connected to a transistor winding associated with the selected isolated voltage output, the commutator being configured to connect a transformer secondary winding to ground in response to the wink signal.

Abstract: One embodiment of the invention is a semiconductor device (500) with a first (500a) and a second (500b) surface, a package including a plastic molding compound (501), and a semiconductor chip (502) inside the package. A first metal sheet (510, 401) covers at least portions of the first package surface (500a), has a thickness (510a, 401a), and is preferably made of copper to operate as a heat spreader. At least one metal connector (511, 402) is in contact with the sheet, has the same thickness as the sheet, and is shaped to be operable as a mechanical spring between sheet and chip. An opening (512, 404) in the sheet is located adjacent to the connector and filled with molding compound. A second metal sheet (520) covers at least portions of the second package surface (500b) and is connected to the chip.