Patents Assigned to Texas Instruments
  • EVENT AND STALL SELECTION
    Publication number: 20060259164
    Abstract: A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • BATTERY PROTECTING CIRCUIT
    Publication number: 20060255768
    Abstract: This invention provides a battery protecting circuit where even if the battery voltage falls nearly to zero volts due to overdischarge or the like while an NMOS transistor set in the power feeding path on the side of the positive electrode of the battery is turned ON/OFF, it is still possible to charge the battery by a constant charging current in a stable way. When the voltage of battery B1 has not reached the voltage needed for generating the driving voltage of NMOS transistors Q1, Q2 in drives 111, 112, the boosting operation of drives 111, 112 is stopped, and PMOS transistor Q3 inserted in a power feeding path different from that of said transistors is turned ON by driver 113. In driver 113, by clamping voltage VDD generated in the power feeding path of PMOS transistor Q3 to a voltage lower than it, driving voltage ZVO of PMOS transistor Q3 is generated without performing a boosting operation.
    Type: Application
    Filed: May 16, 2006
    Publication date: November 16, 2006
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Katsura Yoshio
  • DEPOSITION TOOL CLEANING PROCESS HAVING A MOVING PLASMA ZONE
    Publication number: 20060254614
    Abstract: The present invention provides, in one embodiment, a process for cleaning a deposition chamber (100). The process includes a step (100) of forming a reactive plasma cleaning zone by dissociating a gaseous fluorocompound introduced into a deposition chamber having an interior surface and in a presence of a plasma. The process (100) further includes a step (120) of ramping a flow rate of said gaseous fluorocompound to move the reactive plasma cleaning zone throughout the deposition chamber, thereby preventing a build-up of localized metal compound deposits on the interior surface. Other embodiments advantageously incorporate the process (100) into a system (200) for cleaning a deposition chamber (205) and a method of manufacturing semiconductor devices (300).
    Type: Application
    Filed: July 25, 2006
    Publication date: November 16, 2006
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ignacio Blanco, Jin Zhao, Nathan Kruse
  • METHOD AND SYSTEM OF IDENTIFYING OVERLAYS
    Publication number: 20060259826
    Abstract: A method and system of identifying overlays. At least some of the illustrative embodiments are methods comprising executing a traced program on a target system (the traced program comprising a plurality of overlay programs), obtaining values indicative of which of the plurality of overlays of the traced program has executed on the target system, and displaying on a display device an indication of a proportion of an execution time on the processor of the target system dedicated to each of the plurality of overlay programs.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Gary Swoboda, Oliver Sohm, Brian Cruickshank, Manisha Agarwala
  • EVENT AND STALL SELECTION
    Publication number: 20060259162
    Abstract: A method comprising generating status signals comprising stall and event information associated with a hardware system. The method also comprises multiplexing logic partitioning the status signals into classes according to one or more user-specified partition criteria.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • Automatic network performance data collection and optimization
    Publication number: 20060258295
    Abstract: A method for collecting communication system information from a communication system including a controller and one or more communication devices operating therein includes transmitting a request to the one or more communication devices requesting information regarding a quality of signal(s) received at the one or more communication devices along with geographical location information from the one or more communication devices, and transmitting automatically from the one or more communication devices the signal quality information along with the geographical location information to the controller. A communication device which can automatically provide signal quality and location information is also described, as well as a communication system that can collect signal quality and geographical location information from one or more communication devices operating within the communication system.
    Type: Application
    Filed: May 16, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Tony Wong, Brad Hale
  • Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnects
    Publication number: 20060258142
    Abstract: The present invention provides a method of forming a interconnect barrier layer 100. The method comprises physical vapor deposition of barrier material 200 within an opening 140 located in a dielectric layer 135 of a substrate 110. The method also comprises a RF plasma etching the barrier material 200 deposited in the opening 140 simultaneously with conducting the physical vapor deposition of the barrier material 200.
    Type: Application
    Filed: May 11, 2005
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Asad Haider, Alfred Griffin, Kelly Taylor
  • SYSTEMS AND METHODS FOR CONTROLLING ACCESS TO SECURE DEBUGGING AND PROFILING FEATURES OF A COMPUTER SYSTEM
    Publication number: 20060259828
    Abstract: The present disclosure describes systems and methods for controlling access to secure debugging and profiling features of a computer system. Some illustrative embodiments include a system that includes a processor, and a memory coupled to the processor (the memory used to store information and an attribute associated with the stored information). At least one bit of the attribute determines a security level, selected from a plurality of security levels, of the stored information associated with the attribute. Asserting at least one other bit of the attribute enables exportation of the stored information from the computer system if the security level of the stored information is higher than at least one other security level of the plurality of security levels.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • DISPLAYING CACHE INFORMATION USING MARK-UP TECHNIQUES
    Publication number: 20060259698
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information is from caches on different cache levels associated with a common address. The processor also displays the information by way of a graphical user interface (GUI). The GUI displays a portion of the information using a mark-up technique different from that used to display remaining portions of the information.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Jagadeesh Sankaran, Gary Swoboda
  • PROVIDING CACHE STATUS INFORMATION ACROSS MULTIPLE CACHE LEVELS
    Publication number: 20060259701
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises valid bit and dirty bit information associated with the caches on different cache levels.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda
  • VISUALIZING CONTENTS AND STATES OF HIERARCHICAL STORAGE SYSTEMS ACROSS MULTIPLE CORES
    Publication number: 20060259695
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to provide the information to a user of the software. At least some of the caches on different cache levels are associated with multiple processor cores.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda
  • PRIORITIZING CACHES HAVING A COMMON CACHE LEVEL
    Publication number: 20060259699
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches having a common cache level. The software also causes the processor to prioritize the caches having the common cache level such that the caches are displayable as having different cache levels.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda
  • DETERMINING THE PRESENCE OF A VIRTUAL ADDRESS IN A CACHE
    Publication number: 20060259693
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive status information from circuit logic that collects the status information from caches associated with different processor cores. The software also causes the processor to provide the information to a user of the software. The status information indicates whether one of the caches comprises an entry associated with a virtual address.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank
  • RE-ASSIGNING CACHE LINE WAYS
    Publication number: 20060259703
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. Each of the caches comprises a plurality of cache lines, and each cache line is associated with a way. The software also causes the processor to reassign the way of a cache line to a different way.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank
  • PROVIDING INFORMATION ASSOCIATED WITH A CACHE
    Publication number: 20060259700
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels, the information associated with a common address. The software also causes the processor to provide the information to a user of the software. The information comprises cache level and cache type information associated with a particular cache from one of the different cache levels.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda, Jagadeesh Sankaran
  • VISUALIZING CONTENTS AND STATES OF HIERARCHICAL STORAGE SYSTEMS
    Publication number: 20060259702
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from circuit logic that is adapted to collect the information from caches on different cache levels. At least some of the information from the caches is associated with a common address. The processor also provides the information to a user of the software.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda
  • CROSS-REFERENCING CACHE LINE ADDRESSES WITH CORRESPONDING NAMES
    Publication number: 20060259697
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels. The caches comprise a plurality of cache line addresses, each cache line address associated with a corresponding name. The software causes the processor to display the information on a graphical user interface (GUI), the GUI cross-referencing each of the cache line addresses with a corresponding name.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver SOHM, Brian Cruickshank
  • SELECTIVELY EMBEDDING EVENT-GENERATING INSTRUCTIONS
    Publication number: 20060259750
    Abstract: An information carrier medium containing debugging software that, when executed by a processor, causes the processor to receive information from hardware in communication with the processor, the information indicative of one or more no-operation instructions (NO-OPs) in software code stored on the hardware. The software also causes the processor to selectively replace at least one of the NO-OPs with an event-generating instruction (EGI). When executed, the EGI causes a circuit logic to generate one or more events.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventor: Gary Swoboda
  • DEPOSITION TOOL CLEANING PROCESS HAVING A MOVING PLASMA ZONE
    Publication number: 20060254515
    Abstract: The present invention provides, in one embodiment, a process for cleaning a deposition chamber (100). The process includes a step (100) of forming a reactive plasma cleaning zone by dissociating a gaseous fluorocompound introduced into a deposition chamber having an interior surface and in a presence of a plasma. The process (100) further includes a step (120) of ramping a flow rate of said gaseous fluorocompound to move the reactive plasma cleaning zone throughout the deposition chamber, thereby preventing a build-up of localized metal compound deposits on the interior surface. Other embodiments advantageously incorporate the process (100) into a system (200) for cleaning a deposition chamber (205) and a method of manufacturing semiconductor devices (300).
    Type: Application
    Filed: July 25, 2006
    Publication date: November 16, 2006
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ignacio Blanco, Jin Zhao, Nathan Kruse
  • DETERMINING DIFFERENCES BETWEEN CACHED COPIES OF AN ADDRESS
    Publication number: 20060259696
    Abstract: An information carrier medium containing software that, when executed by a processor, causes the processor to receive information from caches on different cache levels, at least some of the information from caches on different cache levels associated with a common address. The software also causes the processor to determine a difference between the information from caches on different cache levels associated with the common address and to provide the difference to a user of the software.
    Type: Application
    Filed: May 15, 2006
    Publication date: November 16, 2006
    Applicant: Texas Instruments Incorporated
    Inventors: Oliver Sohm, Brian Cruickshank, Gary Swoboda, Jagadeesh Sankaran, Bradley Caldwell