Abstract: The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to about 95 vol % of a first solvent, wherein the first solvent comprises a cyclic ester. A balance of the mixture comprises a second solvent, wherein the second solvent comprises a volatile organic liquid.

Abstract: Techniques for loosely coupling a Global Navigation Satellite System (“GNSS”) and an Inertial Navigation System (“INS”) integration are disclosed herein. A system includes a GNSS receiver, an INS, and an integration filter coupled to the GNSS receiver and the INS. The GNSS receiver is configured to provide GNSS navigation information comprising GNSS receiver position and/or velocity estimates. The INS is configured to provide INS navigation information based on an inertial sensor output. The integration filter is configured to provide blended position information comprising a blended position estimate and/or a blended velocity estimate by combining the GNSS navigation information and the INS navigation information, and to estimate and compensate at least one of a speed bias and a heading bias of the INS navigation information.

Abstract: Over the past few decades, phased locked loops or PLLs have become increasingly common in a variety of microelectronic applications. As such, the PLLs have both decreased in size and increased in speed, following the same trend as all other microelectronics. With this change in size and speed, alternative designs for voltage controlled oscillator tanks or VCOs (and other components of PLLs) are being developed. Here, an LC VCO with a correction circuit (for linearizing the frequency versus control voltage characteristics of the VCO) is described that can allow a small and fast PLL to remain generally stable over a wide range of frequencies.

Abstract: A current source block provided according to an aspect of the present invention provides a substantially constant current even when the provision of the current is switched on and off at different frequencies. The current source block contains a main portion and a replica portion, with each portion having a current source and switches to connect output of the current source to corresponding output nodes. Additional connections are provided to enable the replica portion to counter deviations in the current output of the main portion due to parasitic effects. As a result, the current source block provides a constant current even when switched off/on at different (in particular high) frequencies. Such current source blocks may be used in components such as current steering DACs to obtain a linear response even at high operational frequencies.

Abstract: A digital micromirror device (DMD), a method of manufacturing the DMD and an optical processor incorporating a DMD. In one embodiment, the DMD includes: (1) a first group of micromirrors having a first modulation structure based on a first wavelength of light and a second group of micromirrors having a second modulation structure based on a second wavelength of light, the second wavelength differing from the first wavelength.

Abstract: In at least some embodiments, a communication system includes a receiver having a local oscillator (LO) for each of a plurality of frequency bands. Each LO is controlled by a separate phase-locked loop (PLL) that tracks carrier frequency offset (CFO) using a common phase error (CPE). The CPE is selectively weighted based on at least one inter-band frequency correlation (IFC) coefficient.

Abstract: The present invention provides a blended solvent for solubilizing an ultraviolet photoresist. The blended solvent comprises a mixture of from about 5 vol % to about 95 vol % of a first solvent, wherein the first solvent comprises a cyclic ester. A balance of the mixture comprises a second solvent, wherein the second solvent comprises a volatile organic liquid.

Abstract: In at least some embodiments, a communication device includes a processor and a communication interface coupled to the processor. The communication interface has a programmable current-based hook detection circuit for detecting when a telephonic communication starts and ends.

Abstract: The present invention relates to an integrated electronic device for digital signal processing, which includes a reference clock input for receiving a reference clock, a phase locked loop (PLL), a phase interpolator (PI) coupled to the phase locked loop (PLL) for shifting a phase of an output clock signal of the PLL in a stepwise manner so as to generate a shifted output clock signal (PHI_out), a logic stage for determining the state of the reference clock signal (REF_CLK) multiple times during an edge of the shifted output clock for each phase shift, a storing means for storing information whether or not the determined state of the reference clock signal (REF_CLK) is stable for a phase of the shifted output clock signal (PHI_out), and an interface configured to read out the stored information for determining the jitter of the shifted output clock signal (PHI_OUT).

Abstract: A solid-state image pickup device improves the linearity of signal S1 and increases the saturation level in a solid-state image pickup device with an expanded dynamic range, and a field effect transistor used in the solid-state image pickup device. For the field effect transistor, gate electrode 60 is formed via gate insulating film 50 in a channel forming region of a first semiconductor layer 11 of a first electroconductivity type. A pair of second semiconductor layers (40, 41) of a second electroconductivity type are formed on the surface layer of the first semiconductor layer 11 on both sides of gate electrode 60. A third semiconductor layer 43 of the second electroconductivity type is formed in the first semiconductor layer 11 at a prescribed depth below the channel forming region and is connected to the second semiconductor layer 40. A solid-state image pickup device in which the field effect transistor is used as an amplification transistor is also disclosed.

Abstract: Two transistors of a class D output stage are driven by complementary, variable duty cycle signals PWM+ and PWM?. When the pulse width of the PWM+ signal becomes too narrow for reliable operation of prior art over-current protection circuits sensing the drain to source voltage of FET1 driven by PWM+, a Narrow Pulse Detector generates a signal indicative of this narrow pulse condition. A Negative Current Sense circuit measures the drain to source voltage across FET2 during the much longer conduction time of FET2 driven by PWM?. Because of the energy stored in the series inductor coupled to the output of the class D stage, a negative current flows through this FET2 during its conduction time. The resulting drain to source voltage of FET2 is measured and compared to a threshold. If the voltage indicative of current is over the threshold, and the Narrow Pulse Detector output indicates a narrow pulse condition, then an inhibit signal is generated which reduces current.

Abstract: An integrated circuit structure including multiple thin film resistors having different sheet resistances and TCRs includes a first oxide layer (2) formed on a semiconductor substrate (1), a first thin film resistor (3) disposed on the first oxide layer (2), and a second oxide layer (14) disposed over the first oxide layer (2) and first thin film resistor (3). A second thin film resistor (15) is formed on the second oxide layer (14) and a third oxide layer (16) is formed over the second thin film resistor (15) and the second oxide layer (14). Interconnect metallization elements (12A,B & 22A,B) disposed on at least one of the second (14) and third (16) oxide layers electrically contact the circuit element (4), terminals of the first thin film resistor (3), and terminals of the second thin film resistor (15), respectively, through corresponding contact openings through at least one of the second (14) and third (16) oxide layers.

Abstract: A system and method for providing a high voltage ultrasonic drive signal from an ultrasound transmitter are disclosed herein. An ultrasound transmitter includes a first plurality of drive transistors. A bias network is coupled to at least one transistor of the first plurality of drive transistors. A first switch is coupled to the bias network. The first switch selectively connects a first voltage to the bias network. The first switch is closed when generating an ultrasonic drive signal. The first switch is open when the transmitter is not generating an ultrasonic drive signal.

Abstract: A system and method for power conversion synchronizes multiple phases at a desired phase angle difference. The power conversion involves variable frequency switching, fixed on-time and provides power factor correction. A relative measure of a phase angle difference between two phases permits each phase to be controlled to obtain the desired phase angle difference. The power conversion involves transition mode switching to help reduce switching losses. A phase angle difference detector may be provided for each phase. The various phases may have different inherent frequencies that vary with switching frequency, and are synchronized to an average frequency. Current measures can be taken with a single component, such as a resistor. A maximum frequency control limits period width to avoid high frequency switching. An added switch on time improves input voltage crossover distortion. One or more phases can be deactivated in light load conditions.

Abstract: The present invention provides a high-voltage junction field effect transistor (JFET), a method of manufacture and an integrated circuit including the same. One embodiment of the high-voltage junction field effect transistor (JFET) (300) includes a well region (320) of a first conductive type located within a substrate (318) and a gate region (410) of a second conductive type located within the well region (320), the gate region (410) having a length and a width. This embodiment further includes a source region (710) and a drain region (715) of the first conductive type located within the substrate (318) in a spaced apart relation to the gate region (410) and a doped region (810) of the second conductive type located in the gate region (410) and extending along the width of the gate region (410).

Abstract: A low resistance buried back contact for SOI devices. A trench is etched in an insulating layer at minimum lithographic dimension, and sidewalls are deposited in the trench to decrease its width to sublithographic dimension. Conducting material is deposited in the trench, which serves as a low-resistance contact to the back side of the device. In another embodiment, the trench-fill material is separated from the device by an insulating layer, and serves as a back gate structure.

Abstract: A server for a merchant computer system, the server comprising: a file store for storing a range of audio/video products in respective product files; a dialogue unit having a network connection and operable to invite and receive a client selection from among the products via the network connection; a product reader for reading the product files to generate a digital audio/video signal; a digital signal processing unit having an input connectable to receive the digital audio/video signal from the product reader, a processing core operable to apply a defined level of content degradation to the digital audio/video signal, and an output connected to output the degraded digital audio/video signal from the processing core to the network connection. It is therefore possible for a content provider to change the characteristics of an audio or video data stream supplied over a network to a potential purchaser in a controlled and variable manner.

Abstract: Synchronously stackable double-edge modulated pulse width modulation generators are disclosed. An example pulse width modulation generator includes a ramp generator to generate first and second ramp signals that interact to form a virtual ramp signal; and a comparator module coupled to the ramp generator configured to produce a pulse width modulated signal based on a comparison between the virtual ramp signal and an input signal.

Abstract: A system and method for detecting a broken wire in a communication cable coupling a powered device to power sourcing equipment. Powered Devices (PDs) may be powered by power sourcing equipment via communication cables as in power over Ethernet systems. A current share technique is employed at the Power Sourcing Equipment (PSE) side or the PD side of the Ethernet cable to force currents in twisted pairs of the communication cable to be equal. In one embodiment, first and second power supplies within a PSE are coupled to first and second powered device controllers (PDCs). A characteristic within the system that is indicative of first and second PDC input voltages is measured and the two measured characteristics are compared. If the two measured characteristics are not substantially the same, such indicates the presence of a broken wire.

Abstract: The present invention provides an RF transmission leakage mitigator for use with a full-duplex, wireless transceiver. In one embodiment, the RF transmission leakage mitigator includes an inversion generator configured to provide an RF transmission inversion signal of an interfering transceiver RF transmission to a receiving portion of the transceiver thereby creating a residual leakage signal. Additionally, the RF transmission leakage mitigator also includes a residual processor coupled to the inversion generator and configured to adjust the RF transmission inversion signal of the interfering transceiver RF transmission based on reducing the residual leakage signal to a specified level.