Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract: A method for performing a cell search routine commences by using the Synchronization Channel's (SCH) Primary Synchronization Code (PSC) to acquire slot synchronization to a cell (402). This step will collect a number of hypotheses for frame timing. The method then uses a searcher algorithm such as a sequential dwell searcher that can quickly reject all of the wrong hypotheses gathered in the slot synchronization step, and determine the best hypotheses (404). This cell search routine leads to faster cell acquisition times as compared to some prior art techniques. A receiver (502) that includes a cell searcher (504) that performs the method mentioned above is also described.

Abstract: Methods for gamut mapping and boosting a color saturation of a color signal having multiple colors and a color value for each color. An example method includes mapping each color from a first to a second color space, adjusting each color in the mapped color signal including boosting a color saturation; determining a maximum color value of the color signal; and, in response to a determining that the maximum color value exceeds a maximum displayable color value, setting the color value of the color having the maximum color value to be equal to the maximum displayable color value and scaling color values of colors not having the maximum color value.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: A system and method for providing a continuous wave (“CW”) ultrasonic drive signal and a B-mode ultrasonic drive signal from an ultrasonic transmitter are disclosed herein. An ultrasonic transmitter includes a first shunt transistor and a second shunt transistor. The first shunt transistor shunts positive transmitter output voltage to ground. The second shunt transistor shunts negative transmitter output voltage to ground. The shunt transistors include control inputs that, when modulated, cause the shunt transistors to produce a CW ultrasonic drive signal on a transmitter output. The ultrasonic transmitter also includes a first CW control transistor coupled to the first shunt transistor, and a second CW control transistor coupled to the second shunt transistor. The first and second CW control transistors respectively provide negative and positive CW drive voltage to the first and second shunt transistors.

Abstract: With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate solution has been found. Here, a method and apparatus are provided that can calculate and compensate for bandwidth mismatches in a TI ADC, enabling a high speed, high resolution TI ADC to be produced.

Abstract: According to particular embodiments, a system comprises one or mores light sources, a Digital Micromirror Device (DMD) system, and a controller. A light source is configured to generate light, and the DMD system comprises DMD regions configured to modulate the light. The controller is configured to repeat the following for a number of iterations: instruct each light source to scroll the light across the DMD system at a current amplitude level; instruct one or more DMD regions to operate as one or more active regions that modulate a first portion of the light to generate an image; and instruct the remaining DMD regions to operate as an amplitude modulation region that receives a second portion of the light, the second portion of the light transitioning from a previous amplitude level to the current amplitude level.

Abstract: One embodiment of the invention includes a disk-drive write head fault detection system. The system includes an output stage configured to generate a monitored current through the disk-drive write head. The system also includes an open-circuit fault detector configured to compare a magnitude of a first reference current with a magnitude of the monitored current to detect an open-circuit fault condition associated with the disk-drive write head. The system further includes a short-to-ground fault detector configured to compare a magnitude of a second reference current with the magnitude of the monitored current to detect a short-to-ground fault condition associated with the disk-drive write head.

Abstract: An apparatus providing additional response for a distortion correcting device that receives a first signal at a correcting input and provides a first delayed output signal at an output includes: (a) A first signal combiner coupled with an input and the correcting input. (b) A delay unit coupled with the input provides a second delayed signal to a delayed signal terminal. (c) A second signal combiner coupled with the delayed signal terminal and the output employs the output signal and the second delayed signal to present an error signal at a first error terminal. (d) An adaptive circuit coupled with the input locus, the first signal combiner and the second signal combiner employs provides a supplemental signal to the first signal combiner which employs the input signal and the supplemental signal to present the first signal to reduce the error signal.

Abstract: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.

Abstract: A circuit and a method for biasing a compound cascode current mirror (CCCM) that enables high-voltage swing at the output and accurate current mirroring is presented. The CCCM has mirror transistors and cascode transistors which may be of a different technology kind. The drain-source voltage Vds of the mirror transistor on the input leg of the CCCM is held at a voltage Vov that is generated by the biasing circuit; Vov is the overdrive voltage of the input mirror transistor of the CCCM and the value of Vov is maintained by the bias circuit and a feed-back amplifier such that the mirror transistor remains on the edge of its active region, over manufacture deviations and tracks even over operational conditions such as temperature and supply variations. The feed-back amplifier drives the gates of the cascode transistors and uses its feedback node to hold the Vds at Vov.

Abstract: Estimation of the code size of variable length encoding of quantized DCT coefficients by summation over histogram bins of products of number of bin members and a code size of an average run of zero coefficients coupled with a representative level from the bin. The estimation provides low-complexity feedback for quantization level adjustment to obtain variable length code size target without actual performance of a quantization level plus variable length encoding.

Abstract: The present invention provides proxy browsing on the Internet 16 whereby the user interface of one device, such as a personal computer 10 with a Web browser, causes servers 14 to interact with alternate client devices 20, 24 linked to the Internet 16 that are remotely located from the personal computer. A user may activate a proxy browser on a PC 10, select one or more files or commands from a Web server 14, and download the files or commands directly from the servers to client devices 20, 24. A user of a Web browser 26 may locate and download by proxy a digital sound file stored on a Web server 40 to play on a series of networked digital speakers 54. The user of a Proxy Browser 26 may select a recipe stored on an Web server 40 and send the recipe that has embedded commands to configure networked home appliances 52 to the correct cooking modes.

Abstract: Disclosed herein is a system and method of operating a processor before and after a reset has been asserted. Prior to a reset being asserted the processor operates in one of a plurality of states wherein primary code may be executed by the processor depending on said state. Upon a reset being asserted the processor begins executing code for a reset routine. The processor also executes a process such that the processor operates in the same state it was in prior to the reset upon the reset no longer being asserted.

Abstract: A data output system (100) is disclosed. The data output system (100) includes a number of data output paths (102a-102h) which provide data output signals (DQ0-DQ7) to a data bus. An invert data path 104 provides an invert data signal (INVOUT) that indicates when the data output signals (DQ0-DQ7) have been inverted to reduce the number of transitions on the data bus. A voter circuit (106) determines when data output signal inversion occurs, and includes a local data comparator (132a-132h) associated with each data output path (102a-102h). Each data comparator (132a-132h) compares a current data output signal (D0-D7) with a next data output signal (DN0-DN7), and in response thereto, generates a differential on a pair of data compare lines (138 and 140). The differential on the data compare lines (138 and 140) is amplified by a differential amplifier (136) to generate the invert output signal (INVN) for the following data output cycle.

Abstract: A capillary (10) is provided for use in wire bonding and may be incorporated into a wire bonding machine. The capillary (10) incorporates one or more indicators (100, 105, 110, 113) which may be positioned about the capillary. For example, the indicators may be affixed to an outer surface of the capillary. Sensing of a indicator may be achieved by a detector (160) to determine the angular position of the indicator. This may be used to determine and/or establish the angular alignment of the capillary. The angular alignment may correspond to a desired axis of a wire bonding machine table or lead frame, or to a longitudinal axis of a lead on a lead frame, in order to achieve optimum effectiveness in wire bonding between an integrated circuit chip and the leads of the lead frame. The capillary may be any of a number of differing types including those having circular and non-circular faces.

Abstract: A semiconductor storage device is provided with a storage circuit for a faulty address and a plurality of redundant word lines corresponding to the storage circuit. The storage circuit is adapted to store a faulty address required for selecting a redundant word line. The faulty address is compared with an address input at the time of memory access by a comparator. Using a coincidence signal produced from the comparator and a predetermined address signal contained in the input address, a defect relief circuit selects one of the redundant word lines in place of the faulty word line.

Abstract: Via reliability failure in ULSI devices having aluminum leads is significantly reduced by forming a thin layer of metal, such as Ti, between the aluminum conductor and its antireflection coating. Heating the metal causes it to react with the aluminum and form an intermetallic coating. Via hole formation is achieved by etching. During via formation, if the etch etchs through the antireflection coating, it should stop in the intermetallic layer as opposed to etching into the underlying aluminum conductor. The thin layer of metal may be heated to form the intermetallic during planarization when curing spin on glass, or, a separate anneal may be used with planarization such as by chemical mechanical polish.

Abstract: A method for forming contact vias in order to make electrical connection between conductive interconnection layers is disclosed. The semiconductor slice is processed so as to form the diffusions and underlying interconnection layers using well known techniques. After the deposition and patterning of the last interconnection layer prior to metallization, a layer of platinum or another metal is deposited onto the slice. The slice is sintered to form a silicide film on those portions of the interconnection layers and diffusions which were directly exposed to the sputtered platinum. A layer of phosphorous-doped dielectric is then deposited, followed by a layer of undoped oxide. Photoresist or another conformal material is spun on to the slice, resulting in a planar top surface. The slice is exposed to a plasma etch which etches both the photoresist and the undoped oxide, resulting in a top surface of the undoped oxide which is substantially planar.