Abstract: Differing widths of retimers are developed using differing numbers of individual retimer elements combined together. To maintain synchronous operation, various signals are provided between the individual retimer elements to allow synchronization of the various operations. A first signal is a wired-OR signal that is used for event and operation synchronization. A second set of signals form a serial bus used to transfer proper state information and operation correction data from a master retimer element to slave timer elements. The combination of the wired-OR signal and the serial bus allow the various state machines and operations inside each retimer element to be synchronized, so that the entire width of the link is properly synchronized.

Abstract: A transistor structure with stress enhancement geometry aligned above the channel region. Also, a transistor structure with stress enhancement geometries located above and aligned with opposite sides of the channel region. Furthermore, methods for fabricating integrated circuits containing transistors with stress enhancement geometries.

Abstract: Disclosed examples include ICs and general-purpose I/O circuitry to facilitate interfacing of the IC with a variety of external circuits operating at different supply voltages, in which an integer number N supply drive circuits are individually coupled with a corresponding supply voltage node and selectively connect the corresponding supply voltage node to a general-purpose output node based on a supply drive control signal to allow programmable interfacing of individual general-purpose output pads or pins of the IC with an external circuit at the appropriate signal level.

Abstract: A digital system has a dielectric core waveguide that has a longitudinal dielectric core member. The core member has a body portion and a transition region, with a cladding surrounding the dielectric core member. The body portion of the core member has a first dielectric constant. The transition region of the core member has a graduated dielectric constant value that gradually changes from the first dielectric constant value adjacent the body portion to a third dielectric constant.

Abstract: A falling edge controller includes a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output, an update register control output, and a shift output; a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output; an update register having address and select inputs coupled to the address and select outputs, an update register control input coupled to the update register control output, address outputs coupled to the address inputs, and a select output coupled to the select input; and address circuitry having address inputs coupled to the address outputs, and having an enable output.

Abstract: A conveyor apparatus for a leadframe includes a track defining a longitudinally extending passage through which the leadframe travels. A magnetic clamping system and a plurality of first guide magnets are provided on the track. A gripping device is provided for securing to the leadframe. At least one clamping magnet and a plurality of second guide magnets are secured to the gripping device. The first and second guide magnets cooperate to move the gripping device in a first direction along the length of the passage. The magnetic clamping system and the at least one clamping magnet cooperate to selectively move the gripping device in a second direction perpendicular to the first direction between a first condition spaced from the track to a second condition magnetically fixed to the track.

Abstract: A simple bandgap current generator combines a PTAT (proportional to absolute temperature) base-emitter voltage (VBE) measured across two binary junction devices (?VBE=VBE1?VBE2) with a current that is varied by an nWell resistor with a positive temperature coefficient to produce a CTAT (complementary to absolute temperature) current instead of PTAT reference current. One of the base-emitter voltages is constrained to be VBE1=VBE(1?T). This reduces the temperature dependency of a reference current generated by the bandgap generator. This reference current may be used to generate a bandgap reference voltage by adding an IR drop to a diode voltage or to a base-emitter voltage. The simple bandgap circuit is significantly smaller in size than a precision bandgap circuit, but still provides a voltage and/or a current reference signal having a good accuracy.

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module.

Abstract: An integrated circuit includes an NMOS transistor, a PMOS transistor and a vertical bipolar transistor. The vertical bipolar transistor has an intrinsic base with a band barrier at least 25 meV high at a surface boundary of the intrinsic base, except at an emitter-base junction with an emitter, and except at a base-collector junction with a collector. The intrinsic base may be laterally surrounded by an extrinsic base with a higher dopant density than the intrinsic base, wherein a higher dopant density provides the band barrier at lateral surfaces of the intrinsic base. A gate may be disposed on a gate dielectric layer over a top surface boundary of the intrinsic base adjacent to the emitter. The gate is configured to accumulate the intrinsic base immediately under the gate dielectric layer, providing the band barrier at the top surface boundary of the intrinsic base.

Abstract: A semiconductor device includes a GaN FET with an overvoltage clamping component electrically coupled to a drain node of the GaN FET and coupled in series to a voltage dropping component. The voltage dropping component is electrically coupled to a terminal which provides an off-state bias for the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node of the GaN FET is less than the breakdown voltage of the GaN FET and conducts significant current when the voltage rises above a safe voltage limit. The voltage dropping component is configured to provide a voltage drop which increases as current from the overvoltage clamping component increases. The semiconductor device is configured to turn on the GaN FET when the voltage drop across the voltage dropping component reaches a threshold value.

Abstract: A method for performing a cell search routine commences by using the Synchronization Channel's (SCH) Primary Synchronization Code (PSC) to acquire slot synchronization to a cell (402). This step will collect a number of hypotheses for frame timing. The method then uses a searcher algorithm such as a sequential dwell searcher that can quickly reject all of the wrong hypotheses gathered in the slot synchronization step, and determine the best hypotheses (404). This cell search routine leads to faster cell acquisition times as compared to some prior art techniques. A receiver (502) that includes a cell searcher (504) that performs the method mentioned above is also described.

Abstract: A successive approximation analog to digital converter (SA-ADC) employs a binary-weighted digital to analog converter (DAC) to perform a non-binary search in determining a digital representation of a sample of an analog signal. In an embodiment, a subset of iterations needed to convert an analog sample to a digital value is performed using non-binary search with a radix of conversion less than two. As a result, search windows in iterations corresponding to the non-binary search overlap, and correction of errors due to a comparator used in the SA-ADC is rendered possible. Error correction being possible due to the non-binary search, the comparator is operated in a low-bandwidth, and hence low-power, mode during the non-binary search. The non-binary search in combination with the binary-weighted architecture of the DAC offer several benefits such as for example, less-complex implementation, shorter conversion time, easier and compact layout and lower power consumption.

Abstract: Methods for gamut mapping and boosting a color saturation of a color signal having multiple colors and a color value for each color. An example method includes mapping each color from a first to a second color space, adjusting each color in the mapped color signal including boosting a color saturation; determining a maximum color value of the color signal; and, in response to a determining that the maximum color value exceeds a maximum displayable color value, setting the color value of the color having the maximum color value to be equal to the maximum displayable color value and scaling color values of colors not having the maximum color value.

Abstract: Disclosed herein is a method of manufacturing a semiconductor package with a solder standoff on lead pads that reach to the edge of the package (non-pullback leads). It includes encapsulating a plurality of die on a lead frame strip. The lead frame strip comprises a plurality of package sites, which further comprises a plurality of lead pads and a die pad. The method also includes forming a channel between the lead pads of nearby package sites without singulating the packages. Another step in the method includes disposing solder on the lead pads, the die pad, or the lead pads and the die pads without substantially covering the channel with solder. The manufacturing method further includes singulating the packages.

Abstract: A system and method for providing a continuous wave (“CW”) ultrasonic drive signal and a B-mode ultrasonic drive signal from an ultrasonic transmitter are disclosed herein. An ultrasonic transmitter includes a first shunt transistor and a second shunt transistor. The first shunt transistor shunts positive transmitter output voltage to ground. The second shunt transistor shunts negative transmitter output voltage to ground. The shunt transistors include control inputs that, when modulated, cause the shunt transistors to produce a CW ultrasonic drive signal on a transmitter output. The ultrasonic transmitter also includes a first CW control transistor coupled to the first shunt transistor, and a second CW control transistor coupled to the second shunt transistor. The first and second CW control transistors respectively provide negative and positive CW drive voltage to the first and second shunt transistors.

Abstract: With high speed, high resolution time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches between the various ADC branches can pose a significant problem. Previously, though, no adequate solution has been found. Here, a method and apparatus are provided that can calculate and compensate for bandwidth mismatches in a TI ADC, enabling a high speed, high resolution TI ADC to be produced.

Abstract: According to particular embodiments, a system comprises one or mores light sources, a Digital Micromirror Device (DMD) system, and a controller. A light source is configured to generate light, and the DMD system comprises DMD regions configured to modulate the light. The controller is configured to repeat the following for a number of iterations: instruct each light source to scroll the light across the DMD system at a current amplitude level; instruct one or more DMD regions to operate as one or more active regions that modulate a first portion of the light to generate an image; and instruct the remaining DMD regions to operate as an amplitude modulation region that receives a second portion of the light, the second portion of the light transitioning from a previous amplitude level to the current amplitude level.

Abstract: One embodiment of the invention includes a disk-drive write head fault detection system. The system includes an output stage configured to generate a monitored current through the disk-drive write head. The system also includes an open-circuit fault detector configured to compare a magnitude of a first reference current with a magnitude of the monitored current to detect an open-circuit fault condition associated with the disk-drive write head. The system further includes a short-to-ground fault detector configured to compare a magnitude of a second reference current with the magnitude of the monitored current to detect a short-to-ground fault condition associated with the disk-drive write head.

Abstract: An apparatus providing additional response for a distortion correcting device that receives a first signal at a correcting input and provides a first delayed output signal at an output includes: (a) A first signal combiner coupled with an input and the correcting input. (b) A delay unit coupled with the input provides a second delayed signal to a delayed signal terminal. (c) A second signal combiner coupled with the delayed signal terminal and the output employs the output signal and the second delayed signal to present an error signal at a first error terminal. (d) An adaptive circuit coupled with the input locus, the first signal combiner and the second signal combiner employs provides a supplemental signal to the first signal combiner which employs the input signal and the supplemental signal to present the first signal to reduce the error signal.

Abstract: A method for semiconductor processing is provided, wherein a removal of one or more layers is aided by structurally weakening the one or more layers via ion implantation. A semiconductor substrate is provided having one or more primary layers formed thereon, and a secondary layer is formed over the one or more primary layers. One or more ion species are implanted into the secondary layer, therein structurally weakening the secondary layer, and a patterned photoresist layer is formed over the secondary layer. Respective portions of the secondary layer and the one or more primary layers that are not covered by the patterned photoresist layer are removed, and the patterned photoresist layer is further removed. At least another portion of the secondary layer is removed, wherein the structural weakening of the secondary layer increases a removal rate of the at least another portion of the secondary layer.