Abstract: A self-timed and self-enabled distributed clock is provided for pipeline processor design having functional blocks which include one or more pipeline stages for processing instructions and operations. Each pipeline stage of the processor includes self-timed logic and an enable signal to set up the valid data input to the next pipeline stage. The self-timed logic is used instead of a central, synchronous clock having a predetermined period and provides flexibility of expanding or contracting the clock period in multiple time units depending on the functionality of each pipeline stage. The interfacing between the pipeline stages is handled by a queue buffer which stores incoming instructions to keep the pipeline fully occupied any time there are instructions in the pipeline. A functional unit and its distributed clock are activated only if there is instruction in the pipeline and is otherwise idle.