Patents Assigned to THARAS SYSTEMS
  • A compact processor element for a scalable digital logic verification and emulation system
    Publication number: 20060277234
    Abstract: A logic simulation acceleration processor optimized for multi-value logic level simulation of electronic systems described in hardware description languages.
    Type: Application
    Filed: January 25, 2006
    Publication date: December 7, 2006
    Applicant: THARAS SYSTEMS
    Inventors: Subbu Ganesan, Leonid Broukhis, Ramesh Narayanaswamy, Ian Nixon, Thomas Spencer
  • A scalable system for simulation and emulation of electronic circuits using asymmetrical evaluation and canvassing instruction processors
    Publication number: 20060277019
    Abstract: A scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.
    Type: Application
    Filed: January 26, 2006
    Publication date: December 7, 2006
    Applicant: THARAS SYSTEMS
    Inventors: Subbu Ganesan, Leonid Broukhis, Ramesh Narayanaswamy, Ian Nixon, Thomas Spencer
  • A reconfigurable system for verification of electronic circuits using high-speed serial links to connect asymmetrical evaluation and canvassing instruction processors
    Publication number: 20060277020
    Abstract: A reconfigurable scalable system for verifying electronic circuit designs in anticipation of fabrication by compiling a hardware description to instructions for canvassing processors and instructions for circuit evaluation processors which are scalably interconnected by reconfigurable high-speed serial links to provide simulation and emulation, having deterministically scheduled transfer of circuit signal values among the large number of circuit evaluation processors.
    Type: Application
    Filed: January 26, 2006
    Publication date: December 7, 2006
    Applicant: THARAS SYSTEMS
    Inventors: Subbu Ganesan, Leonid Broukhis, Ramesh Narayanaswamy, Ian Nixon, Thomas Spencer