Abstract: A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Abstract: A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.

Abstract: A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received for the signal, the first bit is set to 1 and when a value of 0 is received for the signal, the second bit is set to 1. Accordingly, by examining the two bits, one may determine whether the signal has attained one or both of 0 and 1 states.

Abstract: A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Abstract: A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.