Abstract: The present disclosure discloses a method for preparing an isolation area of a gallium oxide device, the method comprising: depositing a mask layer on a gallium oxide material; removing a preset portion region of the mask layer; preparing an isolation area in a position, corresponding to the preset portion region, on the gallium oxide material by using a high-temperature oxidation technique, with the isolation area being located between active areas of the gallium oxide device; and removing the remaining mask layer on the gallium oxide material. In the disclosure, the isolation area is prepared by using the high-temperature oxidation technique, which prevents damage to the gallium oxide device during the preparation of the isolation area, thereby achieving isolation between the active areas of the gallium oxide device.

Abstract: A method for preparing an ohmic contact electrode of a GaN-based device. Said method comprises the following steps: growing a first dielectric layer (203) on an upper surface of a device (S1); implanting silicon ions and/or indium ions in a region of the first dielectric layer (203) corresponding to an ohmic contact electrode region, and in the ohmic contact electrode region of the device (S2); growing a second dielectric layer (206) on an upper surface of the first dielectric layer (203) (S3); activating the silicon ions and/or the indium ions by means of a high temperature annealing process, so as to form an N-type heavy doping (S4); respectively removing portions, corresponding to the ohmic contact electrode region, of the first dielectric layer (203) and the second dielectric layer (206) (S5); growing a metal layer (208) on the upper surface of the ohmic contact electrode region of the device, so as to form an ohmic contact electrode (S6).

Abstract: The disclosure provides a method for preparing a self-aligned surface channel field effect transistor, and provides a power device. The method includes the following steps: depositing a first metal mask layer; preparing a first photoresist layer; forming a source area pattern and a drain area pattern; depositing a source metal layer and a drain metal layer on the source area pattern and the drain area pattern; peeling off and removing the first photoresist layer; depositing a second metal mask layer; preparing a second photoresist layer, and forming at least one gate area pattern closer toward the source metal layer by performing exposure and development; removing the first metal mask layer and the second metal mask layer between the source metal layer and the drain metal layer by a wet corrosion; depositing a gate metal layer on the gate area pattern; and peeling off and removing the second photoresist layer.

Abstract: The disclosure provides a method for passivating a silicon carbide epitaxial layer, relating to the technical field of semiconductors. The method includes the following steps: introducing a carbon source and a silicon source into a reaction chamber, and growing a silicon carbide epitaxial layer on a substrate; and turning off the carbon source, introducing a nitrogen source and a silicon source into the reaction chamber, and growing a silicon nitride thin film on an upper surface of the silicon carbide epitaxial layer. The silicon nitride thin film grown by the method has few defects and high quality, and may be used as a lower dielectric layer of a gate electrode in a field effect transistor. It does not additionally need an oxidation process to form a SiO2 dielectric layer, thereby reducing device fabrication procedures.

Abstract: The present disclosure discloses an enhancement-mode field effect transistor. This enhancement-mode field effect transistor includes a substrate, a channel layer formed on an upper surface of the substrate, a source electrode and a drain electrode respectively formed on both sides of the channel layer, and a gate electrode formed on an upper surface of the channel layer, a region outside the corresponding region of the gate electrode in the channel layer is provided with a carrier-free region. Carriers are absent in the carrier-free region, and carriers are present in the remaining portion of the channel layer. The carrier-free region is not disposed below the gate electrode, but is disposed outside the corresponding region of the gate electrode in the channel layer, and the threshold voltage of the device can be regulated by regulating the width and number of the carrier-free region.

Abstract: Disclosed are a preparation method for a diamond-based field effect transistor and a field effect transistor, relating to the technical field of semi-conductors.

Abstract: An unbalanced terahertz frequency doubler circuit with power handling capacity is provided, and the circuit includes a RF input waveguide, a quartz substrate and a RF output waveguide, where one end of the quartz substrate is disposed in a waveguide groove of the RF input waveguide and the other end of the quartz substrate is disposed in a waveguide groove of the RF output waveguide, where an input transition microstrip is disposed on the quartz substrate, and one end of the transition microstrip is connected to an output transition microstrip sequentially through a first transmission microstrip, a low pass filter, a RF matching microstrip and a second transmission microstrip, where anodes of four GaAs-based terahertz frequency multiplier diode groups are connected to the RF matching microstrip, and a cathode at the outermost position of each of the GaAs-based terahertz frequency multiplier diode groups is connected to a grounding quartz strip.

Abstract: An enhanced HFET, comprising a HFET device body.

Abstract: The present application discloses a semiconductor device and a method for forming a p-type conductive channel in a diamond using an abrupt heterojunction, which pertain to the technical field of fabrication of semiconductor devices. The method includes: forming a diamond layer on a substrate; forming one or multiple layers of a heterogeneous elementary substance or compound having an acceptor characteristic on an upper surface of the diamond layer; forming a heterojunction at an interface between the diamond layer and an acceptor layer; forming two-dimensional hole gas at one side of the diamond layer with a distance of 10 nm-20 nm away from the heterojunction; and using the two-dimensional hole gas as a p-type conductive channel. The method enables a concentration and a mobility of carriers to maintain stable at a temperature range of 0° C.-1000° C., thereby realizing normal operation of the diamond device at high temperature environment.

Abstract: The present application discloses an unbalanced terahertz frequency doubler circuit with power handling capacity including a RF input waveguide, a quartz substrate and a RF output waveguide, where one end of the quartz substrate is disposed in a waveguide groove of the RF input waveguide and the other end of the quartz substrate is disposed in a waveguide groove of the RF output waveguide, where an input transition microstrip is disposed on the quartz substrate, and one end of the transition microstrip is connected to an output transition microstrip sequentially through a first transmission microstrip, a low pass filter, a RF matching microstrip and a second transmission microstrip, where anodes of four GaAs-based terahertz frequency multiplier diode groups are connected to the RF matching microstrip, and a cathode at the outermost position of each of the GaAs-based terahertz frequency multiplier diode groups is connected to a grounding quartz strip.

Abstract: The present invention discloses a method for carrying out phosphide in-situ injection synthesis by carrier gas, relating to a synthetic method of semiconductor crystal: step A, shielding inert gas is introduced into a furnace body through a carrier gas intake conduit; step B, a crucible is heated in the furnace body to melt a pre-synthesized raw material in the crucible; step C, the heated shielding inert gas is introduced into the furnace body through the carrier gas intake conduit; step D, a phosphorus source furnace loaded with red phosphorus is moved downwards until an injection conduit of the phosphorus source furnace is submerged in the melt; step E, the red phosphorus is heated by the phosphorus source furnace to produce phosphorus gas, and the phosphorus gas is mixed with the shielding inert gas and then injected into the melt through the injection conduit, and the phosphorus gas reacts with the melt to produce phosphide; and step F, each device is turned off after the synthesis is finished.

Abstract: The invention provides a device and method for continuous VGF crystal growth through rotation after horizontal injection synthesis, and belongs to the technical field of semiconductor crystal synthesis and growth.

Abstract: A method for preparing a cap-layer-structured gallium oxide field effect transistor, includes: removing a gallium oxide channel layer and a gallium oxide cap layer from a passive area of a gallium oxide epitaxial wafer; respectively removing the gallium oxide cap layer corresponding to a source region of the gallium oxide epitaxial wafer and the gallium oxide cap layer corresponding to a drain region of the gallium oxide epitaxial wafer; respectively doping a portion of the gallium oxide channel layer corresponding to the source region and a portion of the gallium oxide channel layer corresponding to the drain region with an N-type impurity; respectively capping an upper surface of the gallium oxide channel layer corresponding to the source region and an upper surface of the gallium oxide channel layer corresponding to the drain region with a first metal layer to respectively form a source and a drain; and forming a gate.

Abstract: The application discloses a parallel seam welding leadless ceramic package, including a ceramic, a sealing ring and a metal cover plate; a back surface of the ceramic is provided with a back grounding metal pattern, and the back grounding metal pattern is provided with several outwardly protruding grounding terminals, a RF signal transmission pad is disposed between every two adjacent grounding terminals, the front grounding metal pattern and the back grounding metal pattern are interconnected by the internal and/or external metallized interconnection holes, the front grounding line and the back grounding metal pattern is interconnected by the internal or external metallized interconnection holes, and the RF signal transmission lines are interconnected to the RF signal transmission pad by a separated external and/or external metallized interconnection hole.

Abstract: A method for manufacturing a graphene transistor based on self-aligning technology, the method comprising: on a substrate (1), forming sequentially graphene material (4), a metal film (5), and photoresist patterns (6) formed by lithography, removing the metal film and the graphene material uncovered by the photoresist, forming an active area, and metal electrodes (7, 8, 9) of a source, a gate, and a drain of the transistor, wherein the source electrode 7 and drain electrode 9 are connected with a metal of the active region, and forming gate photoresist patterns (10) between the source and the drain by lithography, etching off the exposed metal, forming sequentially a seed layer (11), a gate dielectric layer (12), and gate metal (13) on the exposed graphene surface, and finally forming a graphene transistor.

Abstract: Disclosed is a refined white ceramic material, which belongs to the field of ceramic materials for component packaging, and comprises the following raw materials by weight in percentage: aluminum oxide 87-93, magnesium oxide 0.8-5, silicon dioxide 1-6, calcium oxide 0.6-4, titanium dioxide 0.01-0.5, and zirconium dioxide 0.5-3. The method for preparing same comprises: (1) washing aluminum oxide grinding balls and a ball-milling tank, and drying for later use; (2) weighing a solvent NP-10 of 0.5-4 by weight in percentage, and adding the solvent into the ball-milling tank; (3) weighing raw materials, adding the raw materials into the ball-milling tank, and performing ball milling for 72±0.5 h. By means of the refined white ceramic material of the present invention, the obtained ceramic grains have even sizes, small surface roughness, and high fracture resistance performance of ceramic body.

Abstract: Disclosed is a refined white ceramic material, which belongs to the field of ceramic materials for component packaging, and comprises the following raw materials by weight in percentage: aluminum oxide 87-93, magnesium oxide 0.8-5, silicon dioxide 1-6, calcium oxide 0.6-4, titanium dioxide 0.01-0.5, and zirconium dioxide 0.5-3. The method for preparing same comprises: (1) washing aluminum oxide grinding balls and a ball-milling tank, and drying for later use; (2) weighing a solvent NP-10 of 0.5-4 by weight in percentage, and adding the solvent into the ball-milling tank; (3) weighing raw materials, adding the raw materials into the ball-milling tank, and performing ball milling for 72±0.5 h. By means of the refined white ceramic material of the present invention, the obtained ceramic grains have even sizes, small surface roughness, and high fracture resistance performance of ceramic body.