Abstract: A non-volatile memory system includes a NAND flash memory device including at least one NAND flash memory and a memory controller that controls the NAND flash memory, a host device including a file system and a host controller that receives a command from the file system to provide the command to the NAND flash memory device, and a save storage manager that monitors a number and location of run-time bad blocks in the NAND flash memory, monitors a logical address use-state of the file system, and reduces a logical address space which the file system is able to use as the number of the run-time bad blocks is increased.

Abstract: A non-volatile memory system includes a NAND flash memory device including at least one NAND flash memory and a memory controller that controls the NAND flash memory, a host device including a file system and a host controller that receives a command from the file system to provide the command to the NAND flash memory device, and a save storage manager that monitors a number and location of run-time bad blocks in the NAND flash memory, monitors a logical address use-state of the file system, and reduces a logical address space which the file system is able to use as the number of the run-time bad blocks is increased.

Abstract: A non-volatile memory device according to example embodiments includes at least one NAND flash memory and a memory controller configured to control the NAND flash memory. The memory controller comprises a bit counter configured to count a number of first binary digit of each of first to N-th readout page data, the first to N-th readout page data being respectively read by first to N-th test read voltages, a register configured to store first to N-th count values with respect to the first to N-th readout page data output from the bit counter, and a read voltage adjuster configured to compare the first to N-th count values to determine a read voltage, where N is an integer greater than 1.

Abstract: A method of adjusting read voltages for a NAND flash memory device includes an operation of reading first page data from a first page corresponding to a paired page of a second page, an operation of simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page, an operation of performing a bitwise operation on the first page data and the second page data an operation of counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation, and an operation of setting a first read voltage and a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells is a lowest value.

Abstract: A non-volatile memory device according to example embodiments includes at least one NAND flash memory and a memory controller configured to control the NAND flash memory. The memory controller comprises a bit counter configured to count a number of first binary digit of each of first to N-th readout page data, the first to N-th readout page data being respectively read by first to N-th test read voltages, a register configured to store first to N-th count values with respect to the first to N-th readout page data output from the bit counter, and a read voltage adjuster configured to compare the first to N-th count values to determine a read voltage, where N is an integer greater than 1.

Abstract: A method of adjusting read voltages for a NAND flash memory device includes an operation of reading first page data from a first page corresponding to a paired page of a second page, an operation of simultaneously changing the first test read voltage and the third test read voltage to read second page data from a second page, an operation of performing a bitwise operation on the first page data and the second page data an operation of counting a number of memory cells corresponding to a first threshold voltage state and a fourth threshold voltage state by using a result of the bitwise operation, and an operation of setting a first read voltage and a third read voltage as a voltage corresponding to a section in which a change in the number of memory cells is a lowest value.

Abstract: A non-volatile memory system includes a first non-volatile memory device, a second non-volatile memory device that performs a write operation more slowly than the first non-volatile memory device, where the first and second non-volatile memory devices are different types of non-volatile memory devices, and a controller that controls the first and second non-volatile memory devices to concurrently perform the write operation for data input from a host based on a write command signal and that outputs a write completion signal to the host when one of the first and second non-volatile memory devices completes the write operation.

Abstract: A non-volatile memory system includes a NAND flash memory device including a first flash translation layer that performs a garbage collection operation, and a host device including a file system and a second flash translation layer that controls an operation of the NAND flash memory device by interacting with the file system. Here, the host device provides application data in an in-ordered form to the NAND flash memory device. Thus, the non-volatile memory system can perform a random write operation at high speed, and can minimize power consumption due to unnecessary data transfer.

Abstract: A non-volatile memory system includes a first non-volatile memory device, a second non-volatile memory device that performs a write operation more slowly than the first non-volatile memory device, where the first and second non-volatile memory devices are different types of non-volatile memory devices, and a controller that controls the first and second non-volatile memory devices to concurrently perform the write operation for data input from a host based on a write command signal and that outputs a write completion signal to the host when one of the first and second non-volatile memory devices completes the write operation.