Abstract: In general, this disclosure is directed to techniques for remotely controlling a transmitter-side rate adaptation algorithm. According to one aspect, a method includes detecting, with a receiver device, that a packet received from a transmitter is corrupted. The method further includes sending, with the receiver device, a positive acknowledgement for the packet to the transmitter in response to at least detecting that the packet is corrupted. According to another aspect, a method includes determining, with a receiver device, a targeted outcome for a rate adaptation algorithm performed by a transmitter. The method further includes using, with the receiver device, positive acknowledgements to remotely control the rate adaptation algorithm performed by the transmitter based on at least the targeted outcome.

Abstract: In general, this disclosure is directed to techniques for remotely controlling a transmitter-side rate adaptation algorithm. According to one aspect, a method includes detecting, with a receiver device, that a packet received from a transmitter is corrupted. The method further includes sending, with the receiver device, a positive acknowledgement for the packet to the transmitter in response to at least detecting that the packet is corrupted. According to another aspect, a method includes determining, with a receiver device, a targeted outcome for a rate adaptation algorithm performed by a transmitter. The method further includes using, with the receiver device, positive acknowledgements to remotely control the rate adaptation algorithm performed by the transmitter based on at least the targeted outcome.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: The disclosure relates to an automatic level control technique for RF amplifiers in a communication system, such as a wireless communication system. The invention provides an automatic level control technique to compensate for variations in the gain of an RF amplifier, which may be a transmitter amplifier or a receiver amplifier. In accordance with the invention, the gain of the RF amplifier can be controlled as a function of the output of a voltage controlled oscillator (VCO) circuit provided in the communication system. A VCO typically includes a buffer amplifier with a structure similar to that of the RF amplifier used in the transmit or receive side of the RF front-end. By tracking changes in the output of the VCO buffer amplifier, an automatic level control (ALC) input to the RF amplifier can be adjusted to compensate for process- and temperature-based variations in amplifier gain.

Abstract: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.

Abstract: A wireless communication technique enables fast Fourier transforms (FFTs) and inverse fast Fourier transforms (IFFTs) to be performed with reduced latency and reduced memory requirements. In particular, an FFT/IFFT unit receives input data representative of a communication symbol. The FFT/IFFT unit applies an FFT operation to the input data to generate intermediate data. The FFT/IFFT unit stores the intermediate data in a random access memory (RAM). The intermediate data stored in the RAM may override data used as input to the FFT operation. The FFT/IFFT unit selectively addresses the RAM to retrieve the intermediate data in a desired output order. For example, the FFT/IFFT unit may output the intermediate data in the same sequential order as the FFT/IFFT unit received the input data.

Abstract: Demodulation techniques for a wireless communication system make use of a decision feedback equalization (DFE) technique to mitigate the effects of multipath channel characteristics on receiver performance. The techniques may be particularly useful in the demodulation of complementary code keying (CCK) symbols. A demodulator that performs such techniques may include a time-variant or time-invariant matched filter, a feedback intersymbol interference (ISI) canceller, a transform unit, a phase rotation estimator and corrector, a pattern-dependent bias canceller, and a maximum picker for symbol decisions. The transform unit may include a bank of correlators, or alternatively a fast Walsh transform unit.

Abstract: Pairs of second-order filters with feedback and cross coupling may be used to implement pairs of complex poles. The cross coupling may be frequency-dependent cross coupling or frequency-independent cross coupling. Frequency independent cross coupling may include coupling an internal node of a biquad filter. The pairs of second-order filters can be used together to form a complex filter. The complex filter can be used to readily provide higher order poles. The resulting complex filter can achieve higher order poles while offering reduced circuit complexity.

Abstract: A MAC architecture for WLAN stations partitions functionality between a software-based MAC component and a hardware-based MAC component that work together to balance function and performance. In general, the fulcrum for this balance centers on timing requirements. Accordingly, the hardware-based MAC component is designed to handle many of the functions that are processor-intensive and/or must be performed under strict timing constraints. The software-based MAC component is designed to handle many of the functions that are memory-intensive, but present more lenient timing requirements. The software-based MAC component may be configured to provide an efficient and robust interface to the hardware-based MAC component. In particular, the software-based MAC component may format and prioritize packets to be sent over the air interface, and generate a command structure that provides instructions for the hardware-based MAC component to process the packet.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. A device corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The device may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or “ping-ponging” an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: The disclosure relates to an automatic level control technique for RF amplifiers in a communication system, such as a wireless communication system. The invention provides an automatic level control technique to compensate for variations in the gain of an RF amplifier, which may be a transmitter amplifier or a receiver amplifier. In accordance with the invention, the gain of the RF amplifier can be controlled as a function of the output of a voltage controlled oscillator (VCO) circuit provided in the communication system. A VCO typically includes a buffer amplifier with a structure similar to that of the RF amplifier used in the transmit or receive side of the RF front-end. By tracking changes in the output of the VCO buffer amplifier, an automatic level control (ALC) input to the RF amplifier can be adjusted to compensate for process- and temperature-based variations in amplifier gain.

Abstract: Architectures for decoding low density parity check codes permit varying degrees of hardware sharing to balance throughput, power consumption and area requirements. The LDPC decoding architectures may be useful in a variety of communication systems in which throughput, power consumption, and area are significant concerns. The decoding architectures implement an approximation of the standard message passing algorithm used for LDPC decoding, thereby reducing computational complexity. Instead of a fully parallel structure, this approximation permits at least a portion of the message passing structure between check and bit nodes to be implemented in a block-serial mode, providing reduced area without substantial added latency.

Abstract: In general, the disclosure is directed to techniques for enhancing power efficiency and linearity in an RF power amplifier. In accordance with the invention, a combination of different class power amplifiers is implemented in a parallel configuration to overcome the trade-off that exists between power efficiency and linearity. In particular, a class A amplifier and a class B amplifier are arranged in parallel to produce a combined amplifier output for an input signal. With bias voltages set to achieve a desired operating ratio between the class A and class B amplifier, the combined amplifier can provide a high power gain over a larger input range. In addition, the class B amplifier can provide increased power efficiency for larger inputs.

Abstract: In general, the invention is directed to a tunable inductor that makes use of eddy current effect to tune the inductance of an inductor. The tunable inductor may include a spiral or helical inductor in proximity to one or more sets of eddy current coils. Each eddy current coil may be coupled to a corresponding switch that controls whether the eddy current coil is grounded or floating. In operation, a first time-varying current through the inductor induces a first magnetic field that, in turn, induces a time-varying voltage in an eddy current coil. If the eddy current coil is not grounded, an eddy current flows through the eddy current coil. The eddy current, which flows in the opposite direction of the first time-varying current, induces a second magnetic field. The second magnetic field, which opposes the first magnetic field, reduces the inductance of the tunable inductor.

Abstract: A digital front-end for a wireless communication system incorporates gain control, signal detection, frame synchronization and carrier frequency offset (CFO) estimation and correction features configured for use with multiple receive antennas. The digital front-end may be applied to a wireless communication system in which transmitted signals carry a repeated signal pattern, such as orthogonal frequency division multiplexing (OFDM) systems. An example of a repeated signal pattern is the preamble of a signal transmitted according to the IEEE 802.11a wireless local area network (WLAN) standard. The signal detection, frame synchronization, and CFO estimation techniques make use of signals received from multiple antenna paths to provide enhanced performance. The gain control feature may be configured to adjust the gain in steps. The frame synchronization technique may operate as a function of gain control, handling the input signal differently before and after gain adjustment.

Abstract: A wireless communication technique enables equalization, soft demapping and phase error estimation functions to be performed jointly based on multiple observations of a transmitted symbol in wireless communication systems employing receive diversity. Multiple observations of a symbol are obtained from multiple antenna paths in a wireless receiver. Equalization, soft demapping and phase error estimation functions can be integrated within shared hardware, rather than distributed among separate hardware blocks, promoting reduced size, complexity and cost in a wireless receiver.

Abstract: The invention provides a receiver for use in a wireless communication system that substantially reduces mismatch between an in-phase (I) component and a quadrature (Q) component of a received signal. The receiver achieves this by sharing or “ping-ponging” an analog-to-digital converter (ADC) between the I and Q components. By sharing a single pipelined ADC between the I and Q components, both the I and Q components are processed by the same circuitry inside the pipelined ADC thereby eliminating many dominant sources of I-Q mismatch. The pipelined ADC operates at approximately twice the speed as other circuit components. Consequently, I-Q mismatch, which negatively affects performance, may be substantially reduced. At the same time, system complexity, cost, and power dissipation are reduced by eliminating an additional ADC typically used to process the I and Q components in parallel signal paths.

Abstract: An apparatus for dynamic diversity signal reception based upon receiver-side link quality assessments includes two or more antennae. At least one switch is connected to the two or more antennae. A dynamic diversity controller is connected to the at least one switch. The dynamic diversity controller includes a link quality assessor to assess link quality and generate a link characterization value. A diversity configuration selector, responsive to the link characterization value, selectively activates the at least one switch to implement a dynamic diversity configuration. The link quality assessor includes a signal strength analyzer, a modem detector, and/or a MAC layer analyzer to assess the received signal and generate the link characterization value.