Abstract: A network on a chip processor uses uniform addressing for both conventional memory and operand registers. The processor contains a large number of processing elements (e.g., 256). Each processing element has a number (e.g., 200) of operand registers to which it has direct, high-speed (e.g., single clock-cycle) access. Each of these operand registers is also assigned a global memory address, so other processing elements can read or write those operand registers as if they were located in main memory. Software that expects communication between processing elements to happen via memory can use memory-based reads/writes, but gain substantial speed by writing that data directly to the operand registers used for execution of instructions by the target processor.

Abstract: Features that may be computed from a harmonic signal include a fractional chirp rate, a pitch, and amplitudes of the harmonics. A fractional chirp rate may be estimated, for example, by computing scores corresponding to different fractional chirp rates and selecting a highest score. A first pitch may be computed from a frequency representation that is computed using the estimated fractional chirp rate, for example, by using peak-to-peak distances in the frequency distribution. A second pitch may be computed using the first pitch, and a frequency representation of the signal, for example, by using correlations of portions of the frequency representation. Amplitudes of harmonics of the signal may be determined using the estimated fractional chirp rate and second pitch. Any of the estimated fractional chirp rate, second pitch, and harmonic amplitudes may be used for further processing, such as speech recognition, speaker verification, speaker identification, or signal reconstruction.

Abstract: An estimate of a fractional chirp rate of a signal may be computed by using multiple frequency representations of the signal. A first frequency representation may be computed using a first fractional chirp rate and a first score may be computed using the first frequency representation that indicates a match between the first fractional chirp rate and a fractional chirp rate of the signal. A second frequency representation may be computed using a second fractional chirp rate and a second score may be computed using the second frequency representation that indicates a match between the second fractional chirp rate and the fractional chirp rate of the signal. The fractional chirp rate of the signal may be estimated using the first score and the second score, for example, by selecting a fractional chirp rate corresponding to a highest score.

Abstract: An estimate of a pitch of a signal may be computed by using peak-to-peak distances in a frequency representation of the signal. A frequency representation of the signal may be computed, peaks in the frequency representation may be identified, for example, by identifying peaks larger than a threshold value. Peak-to-peak distances may be determined using the locations in frequency of the peaks. The pitch of the signal may be estimated by, for example, estimating cumulative distribution function of the peak-to-peak distances or computing a histogram of the peak-to-peak distances.

Abstract: Systems and methods to perform speaker clustering determine which audio segments appear to include sound generated by the same speaker. Speaker clustering is based on creating a graph in which a node represents an audio segment and an edge between two nodes represents a relationship and/or correspondence that reflects a probability, likelihood, or other indication that the two nodes represent audio segments of the same speaker. This graph is analyzed to detect individual communities of nodes that associate to an individual speaker.

Abstract: Systems and methods for synchronization within a processing system use events and/or signals to indicate whether certain buffers (or other system components) are idle. New tasks may be assigned to individual processing elements once they are deemed idle by virtue of certain buffers or components being idle.

Abstract: Systems and methods may be provided to support memory access by packet communication and/or direct memory access. In one aspect, a memory controller may be provided for a processing device containing a plurality of computing resources. The memory controller may comprise a first interface to be coupled to a router. The first interface may be configured to transmit and receive packets. Each packet may comprise a header that may contain a routable address and a packet opcode specifying an operation to be performed in accordance with a network protocol. The memory controller may further comprise a memory bus port coupled to a plurality of memory slots that are configured to receive memory banks to form a memory and a controller core coupled to the first interface. The controller core may be configured to decode a packet received at the first interface and perform an operation specified in the received packet.

Abstract: A computing system may comprise a plurality of processing devices. In one example, a processing device may comprise a top level router, a device controller and a plurality of processing engines grouped in a plurality of clusters. The top level router may comprise a plurality of high speed communication interfaces to couple the processing device with other processing devices. The device controller may comprise a device controller memory space. Each cluster may have a cluster memory. Each processing engine may comprise an engine memory. The device controller memory space, the cluster memory of all clusters and the engine memory of all processing engines of all processing devices may form a uniform address space for the computing system, which may be addressed using a packet that contains a single destination address in a header of the packet.

Abstract: A computer network may comprise a plurality of computing devices. In one example, a method may be provided for discovering topology of the computer network. The method may comprise sending, by a host computing device of the computing network, a neighbor discovery packet to each network interface of the host that has a connection, receiving a reply packet responding to the neighbor discovery packet, building a neighbor map for all neighbor computing devices to the host, sending a connection discovery packet to each network interface of the host that has a connection, receiving reply packets responding to the connection discovery packet, and building a connection map for connections among computing devices based on the information in the reply packets.

Abstract: Systems and methods may be provided to execute a plurality of computation tasks across a plurality of computing resources of a computing system. In one aspect, a computer-implemented method may execute a software application comprising a plurality of tasks on a computing system. The method may comprise loading the software application into the computing system, assigning the plurality of tasks to a plurality of computing resources of the computing system according to a first assignment, executing the plurality of tasks on the plurality of computing resources according to the first assignment. Each processing resource may be configured to generate and collect system activity monitoring (SAM) data. The method may further comprise collecting the SAM data from the plurality of processing resources, performing an analysis of the first assignment based on the collected SAM data and determining an adjustment to the first assignment based on the analysis.

Abstract: An estimate of a pitch of a signal may be computed by using correlations of frequency portions of a frequency representation of the signal. An initial pitch estimate may be obtained and frequency portions of the frequency representation may be identified using multiples of the initial pitch estimate. Correlations of the frequency portions may be computed, and a score for the initial pitch estimate may be determined using the correlations. A second pitch estimate may be determined using the first score, and the process may be repeated.

Abstract: Voice enhancement and/or speech features extraction may be performed on noisy audio signals. An input signal may convey audio comprising a speech component superimposed on a noise component. The input signal may be segmented into discrete successive time windows including a first time window spanning a duration greater than a sampling interval of the input signal. A transform may be performed on individual time windows of the input signal to obtain corresponding sound models of the input signal in the individual time windows. A first sound model may describe a superposition of harmonics sharing a common pitch and chirp in the first time window of the input signal. Linear fits in time of the sound models over individual time windows of the input signal may be obtained. The linear fits may include a first linear fit in time of the first sound model over the first time window.

Abstract: Systems and methods to implement a platform for processing streams of information, in particular quantification information such as, e.g., real-time sensor data, allow users to define algorithms that are evaluated and re-evaluated continuously as new information becomes available. Revenue received from users and/or other entities that are operating within the platform (or in conjunction with the platform) may be shared with the providers and/or publishers of the streams of information.

Abstract: Disclosed are systems, apparatuses, and methods for implementing a competitive BCM learning rule used in a neural network. Such a method includes identifying a maximally responding neuron with respect to a feature of an input signal. The maximally responding neuron is the neuron in a group that has a response with respect to the feature of the input signal that is greater than a response of each other neuron in the group. Such a method also includes applying a learning rule to weaken the response of each other neuron with respect to the feature of the input signal. The learning rule may also strengthen the response of the maximally responding neuron with respect to the feature of the input signal.

Abstract: Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets.

Abstract: A system and method may be configured to analyze audio information derived from an audio signal. The system and method may track sound pitch across the audio signal. The tracking of pitch across the audio signal may take into account change in pitch by determining at individual time sample windows in the signal duration an estimated pitch and an estimated fractional chirp rate of the harmonics at the estimated pitch. The estimated pitch and the estimated fractional chirp rate may then be implemented to determine an estimated pitch for another time sample window in the signal duration with an enhanced accuracy and/or precision.

Abstract: A system and method may be configured to reconstruct an audio signal from transformed audio information. The audio signal may be resynthesized based on individual harmonics and corresponding pitches determined from the transformed audio information. Noise may be subtracted from the transformed audio information by interpolating across peak points and across trough points of harmonic pitch paths through the transformed audio information, and subtracting values associated with the trough point interpolations from values associated with the peak point interpolations. Noise between harmonics of the sound may be suppressed in the transformed audio information by centering functions at individual harmonics in the transformed audio information, the functions serving to suppress noise between the harmonics.

Abstract: A system and method may be configured to reconstruct an audio signal from transformed audio information. The audio signal may be resynthesized based on individual harmonics and corresponding pitches determined from the transformed audio information. Noise may be subtracted from the transformed audio information by interpolating across peak points and across trough points of harmonic pitch paths through the transformed audio information, and subtracting values associated with the trough point interpolations from values associated with the peak point interpolations. Noise between harmonics of the sound may be suppressed in the transformed audio information by centering functions at individual harmonics in the transformed audio information, the functions serving to suppress noise between the harmonics.

Abstract: A system and method may be configured to reconstruct an audio signal from transformed audio information. The audio signal may be resynthesized based on individual harmonics and corresponding pitches determined from the transformed audio information. Noise may be subtracted from the transformed audio information by interpolating across peak points and across trough points of harmonic pitch paths through the transformed audio information, and subtracting values associated with the trough point interpolations from values associated with the peak point interpolations. Noise between harmonics of the sound may be suppressed in the transformed audio information by centering functions at individual harmonics in the transformed audio information, the functions serving to suppress noise between the harmonics.

Abstract: A neural processing engine may perform processing within a neural processing system and/or artificial neural network. The neural processing engine may be configured to effectively and efficiently perform the type of processing required in implementing a neural processing system and/or an artificial neural network. This configuration may facilitate such processing with neural processing engines having an enhanced computational density and/or processor density with respect to conventional processing units.