Patents Assigned to The International Business Machines Corporation
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Patent number: 9158462Abstract: In one embodiment, an apparatus includes a processor and logic integrated with and/or executable by the processor, the logic being configured to write one or more data sets to a magnetic tape volume, the magnetic tape volume being configured to store data thereon, determine metadata corresponding to the one or more written data sets, and write the metadata corresponding to the one or more written data sets to a tape volume access block (TVAB) stored to the magnetic tape volume after a last written data set. In yet another embodiment, a method for managing a magnetic tape volume includes auditing a magnetic tape volume to determine a plurality of data sets stored thereto, determining metadata corresponding to the plurality of data sets, storing the metadata corresponding to the plurality of data sets to a TVAB, and writing the TVAB to the magnetic tape volume after a last written data set.Type: GrantFiled: January 9, 2014Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Gavin S. Johnson, Jon A. Lynds
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Patent number: 9158537Abstract: According to one embodiment of the present disclosure, hardware initialization code and error action information are retrieved from separate storage areas. The hardware initialization code includes code that initializes a device, and also includes placeholders corresponding to actions that are performed when the device fails initialization. Likewise, the error action information describes the actions that are performed when the device fails initialization. The error action information is converted into macros that include lines of code. As such, the error action placeholders are matched to the macros and, in turn, each of the error action placeholders is replaced with the lines of code corresponding to the matched macros.Type: GrantFiled: January 14, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Daniel M. Crowell, John Farrugia, Michael J. Jones, David Dean Sanner
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Patent number: 9158648Abstract: A system facilitates reporting product status information using a visual code. The system includes a code generator and a communication device. The code generator reports a product status with aggregate information in a visual code. In order to achieve this functionality, the code generator recognizes a status event trigger for a product. The code generator also compiles the aggregate information in response to the status event trigger for the product. The aggregate information includes product status information and product identification information. The code generator also generates the visual code representative of the aggregate information. The communication device facilitates communication of the visual code to a user.Type: GrantFiled: September 14, 2012Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: David B Bartlett, James C Fletcher
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Patent number: 9159088Abstract: Location-aware preference and restriction based customized menu may be generated, for example, by obtaining a list of preferences and restrictions, tracking a dietary intake, determining a list of foods available at current location, and generating a list of recommended foods from the current location based on the list of preferences and restrictions, and the tracked dietary intake.Type: GrantFiled: June 30, 2011Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Tawanna R. Dillahunt, Peter K. Malkin, Mark N. Wegman
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Patent number: 9159692Abstract: Various embodiments include wafer level chip scale package (WLCSP) structures and methods of tuning such structures. In some embodiments, the WLCSP structure includes: a printed circuit board (PCB) trace connection including at least one PCB ground connection connected with a PCB ground plane; a set of ground solder balls each contacting the printed circuit board trace connection; a set of chip pads contacting each of the ground solder balls in the set of ground solder balls; a chip ground plane connecting the set of chip pads; and a signal interconnect interposed between two of the set of ground solder balls, the signal interconnect including: a signal trace connection electrically isolated from the PCB ground plane; a signal ball contacting the signal PCB trace connection; a chip pad contacting the signal ball, and a signal trace connection on a chip contacting the chip pad.Type: GrantFiled: October 21, 2014Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Hanyi Ding, Richard S. Graf, Gary R. Hill, Wayne H. Woods, Jr.
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Patent number: 9160622Abstract: Determining a system configuration for performing a collective operation on a parallel computer that includes a plurality of compute nodes, the compute nodes coupled for data communications over a data communications network, including: selecting a system configuration on the parallel computer for executing the collective operation; executing the collective operation on the selected system configuration on the parallel computer; determining performance metrics associated with executing the collective operation on the selected system configuration on the parallel computer; selecting, using a simulated annealing algorithm, a plurality of test system configurations on the parallel computer for executing the collective operation, wherein the simulated annealing algorithm specifies a similarity threshold between a plurality of system configurations; executing, the collective operation on each of the test system configurations; and determining performance metrics associated with executing the collective operation oType: GrantFiled: February 7, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Charles J. Archer, James E. Carey, Philip J. Sanders, Brian E. Smith
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Patent number: 9160832Abstract: Embodiments of the invention relate to management of notifications responsive to the arrival and departure of mobile devices in a defined area. A prioritized list is shared among mobile devices in a defined area. Upon detection, mobile devices add their respective selected notifications to the prioritized list. A mobile device entering the defined area receives the prioritized list and in response to detecting a shared selected notification on the prioritized list, one of the mobile devices in the area changes its selected notification to an alternative notification. A second mobile device entering the defined area would likewise receive the prioritized list and change its selected notification to a second alternative notification responsive to a shared selected notification on the list. At such time as a device leaves the area, the list is again updated and all notifications exclusive to the device are removed from the list.Type: GrantFiled: January 9, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Shawn P. Mullen, Jessica C. Murillo, Johnny M. Shieh
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Patent number: 9158706Abstract: Space of a data storage memory of a data storage memory system is reclaimed by determining heat metrics of data stored in the data storage memory; determining relocation metrics related to relocation of the data within the data storage memory; determining utility metrics of the data relating the heat metrics to the relocation metrics for the data; and making the data whose utility metric fails a utility metric threshold, available for space reclamation. Thus, data that otherwise may be evicted or demoted, but that meets or exceeds the utility metric threshold, is exempted from space reclamation and is instead maintained in the data storage memory.Type: GrantFiled: October 31, 2011Date of Patent: October 13, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael T. Benhase, Evangelos S. Eleftheriou, Lokesh M. Gupta, Robert Haas, Xiao-Yu Hu, Matthew J. Kalos, Ioannis Koltsidas, Roman A. Pletka
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Patent number: 9159920Abstract: An example embodiment disclosed is a process for fabricating a phase change memory cell. The method includes forming a bottom electrode, creating a pore in an insulating layer above the bottom electrode, depositing piezoelectric material in the pore, depositing phase change material in the pore proximate the piezoelectric material, and forming a top electrode over the phase change material. Depositing the piezoelectric material in the pore may include conforming the piezoelectric material to at least one wall defining the pore such that the piezoelectric material is deposited between the phase change material and the wall. The conformal deposition may be achieved by chemical vapor deposition (CVD) or by atomic layer deposition (ALD).Type: GrantFiled: July 24, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Catherine A. Dubourdieu, Martin M. Frank, Bipin Rajendran, Alejandro G. Schrott
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Patent number: 9158711Abstract: Creating a computer program product or a computer system to execute a frame management instruction which identifies a first and second general register. The first general register contains a frame management field having a key field with access-protection bits and a block-size indication. If the block-size indication indicates a large block then an operand address of a large block of data is obtained from the second general register. The large block of data has a plurality of small blocks each of which is associated with a corresponding storage key having a plurality of storage key access-protection bits. If the block size indication indicates a large block, the storage key access-protection bits of each corresponding storage key of each small block within the large block is set with the access-protection bits of the key field.Type: GrantFiled: December 5, 2014Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Dan F Greiner, Charles W Gainey, Jr., Lisa C Heller, Damian L Osisek, Timothy J Slegel, Gustav E Sittmann
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Patent number: 9158694Abstract: A method, information processing device, and computer program product mitigate busy time in a hierarchical store-through memory cache structure. A cache directory associated with a memory cache is divided into a plurality of portions each associated with a portion memory cache. Simultaneous cache lookup operations and cache write operations between the plurality of portions of the cache directory are supported. Two or more store commands are simultaneously processed in a shared cache pipeline communicatively coupled to the plurality of portions of the cache directory.Type: GrantFiled: October 31, 2012Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Deanna P. Berger, Michael F. Fee, Christine C. Jones, Arthur J. O'Neill, Diana L. Orf, Robert J. Sonnelitter, III
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Patent number: 9160746Abstract: A method may comprise maintaining by a computer system connected to a network an indication of availability dates and times of one or more output devices connected to the network. The computer system may receive an output device invitation indicating an output device to reserve for a meeting conducted over a conferencing system and determine whether the output device is available for reservation during a date and time period of the meeting. The computer system may be communicating over the network to the output device activation information indicating that the output device is to become active at a predetermined date and time related to the date and time period of the meeting and login information including a credential for the output device to use for logging into the conferencing system for the meeting.Type: GrantFiled: January 31, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Darryl M Adderly, Christopher T Carlin, Michelle Davis, Dale J Heeks, Ryan E Smith
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Patent number: 9158468Abstract: Methods, systems, and computer program products are provided for deduplicating data mapping a plurality of file blocks of selected data to a plurality of logical blocks, deduplicating the plurality of logical blocks to thereby associate each logical block with a corresponding physical block of a plurality of physical blocks located on a physical memory device, two or more of the corresponding physical blocks being non-contiguous with each other, determining whether one or more of the corresponding physical blocks are one or more frequently accessed physical blocks being accessed at a frequency above a threshold frequency and being referred to by a common set of applications, and relocating data stored at the one or more frequently accessed physical blocks to different ones of the plurality of physical blocks, the different ones of the plurality of physical blocks being physically contiguous.Type: GrantFiled: January 2, 2013Date of Patent: October 13, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Duane M. Baldwin, Clodoaldo Barrera, Mihail C. Constantinescu, Sandeep R. Patil, Riyazahamad M. Shiraguppi
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Patent number: 9159051Abstract: A SEF grammar is created to be used with the Java CC program to autogenerate a SEF parser. The SEF parser can be run with specially written X12 code on any SEF file to automatically create an EDI object model for that SEF file. A programmer can then write application code to use the EDI object model to parse an EDI document that the SEF file describes and generate in memory an EDI object model instance for that EDI document. The application code is also used to employ the EDI object model instance to efficiently process the EDI document's EDI transaction. In addition, the application code is used to employ the EDI object model on the EDI object model instance to emit an EDI document for further use.Type: GrantFiled: August 20, 2008Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventor: Michael Perham
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Patent number: 9158588Abstract: Embodiments of thread binding are provided. An aspect includes generating a thread layout for an application. Another aspect includes determining a task count for the application; determining a task rank for each task of the task count; determining a thread count for each task associated with the application, wherein a thread count for a first task associated with the application is unequal to a thread count of a second task associated with the application; and indicating one or more preferred processors of a plurality of processors for each task associated with the application. Another aspect includes allocating system for each of the tasks of the application based on the thread layout. Another aspect includes affinitizing the tasks by generating child threads for each of the tasks, wherein a number of threads generated for each task corresponds to the thread count for the task in the thread layout.Type: GrantFiled: December 3, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: James Abeles, Farid A. Parpia
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Patent number: 9155320Abstract: Operating a database system comprises: storing a database table comprising a plurality of rows, each row comprising a key value and one or more attributes; storing a primary index for the database table, the primary index comprising a plurality of leaf nodes, each leaf node comprising one or more key values and respective memory addresses, each memory address defining the storage location of the respective key value; creating a new leaf node comprising one or more key values and respective memory addresses; performing a memory allocation analysis based upon the lowest key value of the new leaf node to identify a non-full memory page storing a leaf node whose lowest key value is similar to the lowest key value of the new leaf node; and storing the new leaf node in the identified non-full memory page.Type: GrantFiled: March 16, 2012Date of Patent: October 13, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Markku J. Manner, Simo A. Neuvonen, Vilho T. Raatikka
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Patent number: 9159602Abstract: Apparatus and methods are provided for high density packaging of semiconductor chips using silicon space transformer chip level package structures, which allow high density chip interconnection and/or integration of multiple chips or chip stacks high I/O interconnection and heterogeneous chip or function integration.Type: GrantFiled: August 19, 2009Date of Patent: October 13, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Paul S. Andry, John M. Cotte, John U. Knickerbocker, Cornelia K. Tsang
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Patent number: 9159028Abstract: Provided are techniques for computing a task result. A processing data set of records is created, wherein each of the records contains data specific to a sub-task from a set of actual sub-tasks and contains a reference to data shared by the set of actual sub-tasks, and wherein a number of the records is equivalent to a number of the actual sub-tasks in the set of actual sub-tasks. With each mapper in a set of mappers, one of the records of the processing data set is received and an assigned sub-task is executed using the received one of the records to generate output. With a single reducer, the output from each mapper in the set of mappers is reduced to determine a task result.Type: GrantFiled: January 11, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Yea J. Chu, Dong Liang, Jing-Yun Shyr
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Patent number: 9158606Abstract: Avoiding failure repetition in data processing includes storing a sequence of circumstances leading up to a previous failure, monitoring circumstances in a current process, matching a sequence of circumstances in the current process to a stored sequence of circumstances, and applying rules to determine if the current process should proceed.Type: GrantFiled: January 22, 2010Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Julien Charles Horn, Roger Gordon Lewis, Alan Clive Robinson, Andrew Wright
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Patent number: 9158530Abstract: Assigning severity to a software update, including: receiving, by an update manager, version information for a software application from a computing system, the version information describing a version of the software application installed on the computing system; determining, by the update manager, a severity level of one or more available updates for the software application in dependence upon the version information and update version information; and providing, by the update manager to the computing system, the severity level for each of the one or more available updates.Type: GrantFiled: October 22, 2013Date of Patent: October 13, 2015Assignee: International Business Machines CorporationInventors: Albert D. Bennah, Adrian X. Rodriguez