Abstract: A method of fabricating and a structure of a merged multi-fin finFET. The method includes forming single-crystal silicon fins from the silicon layer of an SOI substrate having a very thin buried oxide layer and merging the end regions of the fins by growing vertical epitaxial silicon from the substrate and horizontal epitaxial silicon from ends of the fins such that vertical epitaxial silicon growth predominates.

Abstract: Phase and frequency detectors and techniques are disclosed. For example, apparatus comprises a first circuit for receiving first and second clock signals and for generating at least one signal indicative of a phase difference between the first and second clock signals. The apparatus also comprises a second circuit for receiving the at least one signal generated by the first circuit and, in response to the at least one received signal, generating at least one output signal, wherein a frequency associated with the at least one output signal is proportional to a frequency difference between the first and second clock signals.

Abstract: A phased-array transmitter and receiver that may be effectively implemented on a silicon substrate. The transmitter distributes to front-ends, and the receiver combines signals from front-ends, using a power distribution/combination tree that employs both passive and active elements. By monitoring the power inputs and outputs, a digital control is able to rapidly provide phase and gain correction information to the front-ends. Such a transmitter/receiver includes a plurality of radio frequency (RF) front-ends and a power splitting/combining network that includes active and passive components configured to distribute signals to/from the front-ends.

Abstract: A method for verifying the integrity of a communication link is disclosed herein. In selected embodiments, such a method may include detecting, during normal operation of a communication link, a condition indicative of a high failure rate (HFR) on the communication link. The method may further include placing the communication link in an HFR state as a result of the condition. While in HFR state, the method may repeatedly transmit test I/Os over the communication link. The method may then automatically exit HFR state and resume normal operation on the communication link when one or more of the following has occurred: a selected number of test I/Os have been successfully transmitted over the communication link, and a number of test I/Os have been successfully transmitted over the communication link for a selected period of time. A corresponding system, apparatus, and computer program product are also disclosed and claimed herein.

Abstract: A method and system are provided to classify and convey data to satisfy a client request. The classification system is a two dimensional data classification system, including a first dimension pertaining to subject matter and a second dimension pertaining to data security. A partition is dynamically created, and data that satisfies the request populates the created partition to convey parsed data based satisfying both dimensions of the request.

Abstract: A nameplate for power capping a computer including a mounting surface; a module integrated in the mounting surface for providing a machine-readable designation of a power cap for a particular computer; a human readable designation of a power cap for the particular computer integrated in the mounting surface; and a mount for attaching the mounting surface to a chassis of the particular computer such that the human readable designation of a power cap is exposed.

Abstract: A mechanism programming a direct memory access engine operating as a multithreaded processor is provided. A plurality of programs is received from a host processor in a local memory associated with the direct memory access engine. A request is received in the direct memory access engine from the host processor indicating that the plurality of programs located in the local memory is to be executed. The direct memory access engine executes two or more of the plurality of programs without intervention by a host processor. As each of the two or more of the plurality of programs completes execution, the direct memory access engine sends a completion notification to the host processor that indicates that the program has completed execution.

Abstract: Systems, methods and articles of manufacture are disclosed for building and executing analytics solutions. Such a solution may provide a comprehensive analytics solution (e.g., a risk assessment, fraud detection solution, dynamic operational risk evaluations, regulatory compliance assessments, etc.). The analytics solution may perform an analytics task using operational data distributed across a variety of independently created and governed data repositories in different departments of an organization. A framework is disclosed which allows a user (e.g., a risk analyst) to compose analytical tools that can access data from a variety of sources (both internal and external to an enterprise) and perform a variety of analytic functions.

Abstract: A system for injecting business content dynamically based on the context of the user. A media content analysis tool may be used to analyze existing media to identify features and insert tags based on the content and/or time. A media content orchestrator may be used to author scriplets containing product advice for the media stream to insert and associate scriplets to tags in the media stream. The media player, equipped with a codec for the new media format, performs functions such as browsing product information, places orders, or the like.

Abstract: Exemplary embodiments of this invention provide a method that includes estimating an empirical distribution of a metric for a company. The method includes estimating a distribution of the metric for a plurality of companies. The method further includes determining whether the company is an outlier, based on the empirical distribution of the metric for the company and the distribution of the metric for the plurality of companies, and generating at least one recommendation based determining whether the company is an outlier.

Abstract: A method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions. The programming instructions are operable to receive a tool error output determined by a code inspection tool and select at least one defect classification mapping profile based on the code inspection tool. Additionally, the programming instructions are operable to map the tool error output to one or more output classifications using the selected at least one defect classification mapping profile and generate at least one report based on the one or more output classifications.

Abstract: A key hole structure and method for forming a key hole structure to form a pore in a memory cell. The method includes forming a first dielectric layer on a semiconductor substrate having an electrode formed therein, forming an isolation layer on the first dielectric layer, forming a second dielectric layer on the isolation layer, and forming a planarization stop layer on the second dielectric layer. The method further includes forming a via to extend to the first dielectric layer and recessing the isolation layer and the stop layer with respect to the second dielectric layer, depositing a conformal film within via and over the stop layer, forming a key hole within the conformal film at a center region of the via such that a tip of the key hole is disposed at an upper surface of the second dielectric layer, and planarizing the conformal film to the stop layer.

Abstract: A method to at least partially isolate a net of a circuit design is provided and includes testing a timing characteristic of a circuit design, identifying from a result of the testing a net of the circuit design to be at least partially isolated from an adjacent net and determining a percentage of the identified net to be partially isolated.

Abstract: One embodiment of the invention provides a multi-layered ceramic package. The ceramic package includes a signal layer having a plurality of signal lines and a mesh reference layer parallel to the signal layer. The mesh reference layer includes a plurality of intersecting reference lines of varying reference-line width in the plane of the mesh layer. The mesh reference lines may be widened in locations of probable signal cross-talk. Other embodiments of the invention include software for optimizing a ceramic package design by selectively widening mesh lines in regions of probable cross-talk, and systems for designing and manufacturing such a ceramic package.

Abstract: A computer implemented method, apparatus, and computer program product for managing task data. A task advisor identifies a set of queries and a set of data sources mapped to a task type in a mapping entry. The task type is associated with a selected task. The mapping entry maps the task type to the set of queries. The set of queries is mapped to the set of data sources. The task advisor sends each query in the set of queries to a corresponding data source in the set of data sources. The task advisor aggregates the data received from the set of data sources in response to the set of queries. A user may utilize the aggregated data to complete the selected task.

Abstract: A method and system of calibrating estimates for software projects is provided. More particularly, a method and system is provided to continuously provide calibration estimation and improvement options across a software integration life cycle. The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable to: compare actual data associated with a phase of a project to expected results used to develop a strategic development plan for the project; and calibrate efforts in the strategic development plan for future activities of the project based on the actual data.

Abstract: A device and method for providing an integrated circuit with a unique identification. The device is usable on an integrated circuit (IC) for generating an identification (ID) identifying the IC and includes a plurality of identification cells each utilizing one of a four wire resistor, thin film resistors, and an inverter pair. A measurement circuit measures a parameter of each cell and is utilized in generating the ID in response thereto.

Abstract: A method, system and article of manufacture are disclosed for establishing a connection between a plurality of nodes in a communication network, the plurality of nodes including at least first and second nodes. The method comprises the steps of verifying availability of the second node by the first node; and sending an exchange identification request by the first node to the second node, this request including information related to protocols supported by the first node. An exchange identification response is received by the first node from the second node, this response including information related to protocols supported by the second node. Also, the verifying step includes the steps of sending a request to the second node to initiate a link level connection between the first node and the second node, and confirming this connection upon receiving a response from the second node.

Abstract: A method and system for managing traffic between a first provider edge and a second provider edge in a network. The network includes logical paths between the first provider edge and the second provider edge. For each logical path, jitter, packet delay, and packet loss are identified. For each logical path, a path usage is calculated as a function of the identified jitter, packet delay, and packet loss. Most recent data received by the first provider edge is transmitted to the second provider edge via a selected logical path that has a highest path usage for which transmitting the received most recent data does not result in the selected logical path managing a higher percentage of network traffic than is dictated by the highest usage value for the selected logical path.

Abstract: Pixel sensor cells, method of fabricating pixel sensor cells and design structure for pixel sensor cells. The pixel sensor cells including: a photodiode body in a first region of a semiconductor layer; a floating diffusion node in a second region of the semiconductor layer, a third region of the semiconductor layer between and abutting the first and second regions; and dielectric isolation in the semiconductor layer, the dielectric isolation surrounding the first, second and third regions, the dielectric isolation abutting the first, second and third regions and the photodiode body, the dielectric isolation not abutting the floating diffusion node, portions of the second region intervening between the dielectric isolation and the floating diffusion node.