Abstract: A memory cell having three MOS transistors and four external connecting lines, and suitable for fabrication in an array of memory cells forming rows and columns on an LSI chip, is organized into a stack of chips to form a three dimensional random-access read-write memory system. The memory array is organized so that each memory cell on the chip provides capacitive storage for a binary digit of a different word and a single digit is written into or read from a selected memory cell of a single chip or array as a word is written into, or read from, the memory system. The memory cells of each chip are arranged in a matrix of rows and columns, whereby a limited number of semiconductors are required in the memory array to form the capacitive storage memory cells and connecting selection circuitry.