Abstract: There is provided a circuit and method for subtracting floating point numbers which are represented by binary bits. In this circuit, the smaller number (minuend) in one register is arranged so that the complement thereof is denormalized and added to the subtrahend (i.e. larger number) and the result of the addition is returned to the original register. At that time, the signal stored in the register is renormalized. In this circuit, the number of guard bits required to guarantee round off accuracy is only two.

Abstract: This invention is directed at an apparatus and method for detecting zero operand information and which also serves to detect trailing zeros. This circuit has application in computer circuitry, systems or the like wherein elongated information trains represented by multiple words of multiple bits are multiplied by equally long information trains. In many cases, the trains comprise a plurality of trailing zeros which, in accordance with the operation of this circuit, can be detected whereby the multiplication operation can be significantly speeded by avoiding unnecessary multiplication by zeros without loss of accuracy.

Abstract: A disk drive control system incorporating an internal microprocessor and internal testing capabilities. The disk drive control system is capable of simulating drive operation without carriage motion so as to test substantially all functional subsystems of the disk drive. The test technique comprises the exercising of subsystems and a diagnosis of operations according to a hierarchy of interdependence of subsystem operation.

Abstract: A signal amplitude equalizer circuit, having linear phase, for reforming high density magnetically recorded read-back signals to remove peak shift and the resulting errors caused thereby. The equalizer circuit employs series balanced differential amplifier circuits in connection with properly terminated delay lines across the amplifier output terminals to provide an adjustable transfer function that transforms the readhead signal, that follows an exponential frequency spectra curve, into a cosine power frequency spectra curve which, in the time domain, possesses a sufficiently narrow base to eliminate peak shift and its resulting amplitude decay.

Abstract: An electronic tachometer that includes an integrator for producing a speed signal by integrating a signal representative of acceleration of a body and a differentiator for producing a speed signal by differentiating a signal representative of the position of the body, the differentiator being formed by a passive RC circuit and operatively associated with circuitry for alternately supplying to the differentiator two signals representative of position, one of which is inverted so that signals of a single polarity are supplied to the differentiator, and further circuitry for connecting the differentiator output to the integrator feedback circuitry so as periodically to update or reset the speed signal produced by the integrator, which is formed by an operational amplifier having a capacitive feedback which is shunted by a resistor when the differentiator output is active to update the integrator.

Abstract: There is provided an error detection and correction circuit which is optimized in terms of the operation, part count and the like. This invention includes parity generator circuitry to generate parity signals in accordance with a variation of the Hamming Code in response to the application of a plurality of input data bits. The parity signals are applied to a memory bus during a write cycle. During a read cycle, the parity generators produce a parity error signal, if appropriate, to indicate an error in parity. The error correction circuit receives the data bits from the memory (or memory bus) along with the parity error signals generated by the parity generator circuit portion. The data signals and parity error signals are gated together and supplied to Exclusive-OR gates. If an error is indicated by the level of the input signal, the Exclusive-OR gate converts the signal thereby correcting the erroneous data bit.

Abstract: A rotor for an axial flow combine which is adapted to coact with conventional grate means in said combine, said rotor having on the forward end thereof interrupted infeed flight means which are spiral segments spaced both axially and circumferentially from each other, and certain of the leading ends of said flight segments in the direction of rotation of the rotor extending radially a limited distance beyond the outer edges of said segments to provide aggressive engagement of said segments with crop material being delivered to said flight from conventional elevator mechanism and the like normally employed in combines.

Abstract: Peripheral devices of a microprocessor controlled system initiate service request signals which are sent to a system controller over a single dedicated request line. Such request signals are accepted by the system controller on a priority basis, with only one service request signal being honored at any given time. Once honored, the system controller addresses the peripheral device and accepts a vector request word therefrom. The vector request word is then used by the system controller to generate an index signal to select a microaddress of the microroutine to be used to service a peripheral device's request.

Abstract: A voltage regulation loop for the rejection of line frequency ripple of 0-180 Hz in an inverter power supply is disclosed. The loop includes an error amplifier (E), a pulse-width modulator (P), an inverter (I), a second summing node (N.sub.2), an output filter (F), and a feedback loop back to a first summing node N.sub.1 at the error amplifier. The novel pulse-width modulator is non-linearly operated to provide an improved rejection of the power supply's line frequency ripple and an improved stability.

Abstract: Apparatus for scaling addresses received by a memory module in a modular requestor-memory system in which standard memory modules may be of a discretely variable size and utilized in a plurality of positions in an overall contiguous memory addressing scheme. In particular, this scaling apparatus enables a modular memory which is only partially populated, i.e., only able to respond to a subset of the set of all addresses available, to be located in any one of several positions representing different addressing ranges. This is accomplished without modification of the memory module itself. The memory module knows its discrete capacity, or size, by virtue of the population of the memory array storage locations (array cards) contained therein. The memory module then uses this information to scale, or strip off, the appropriate number of bits from the gross address to allow addressing of the restricted number of memory locations present in the memory module.

Abstract: In a digital information storage system or the like, start up power sequencing for independently operable machines such as disk drives each equipped with a microprocessing unit is provided through a simplified power sequencing circuit. The power sequencing circuit is operatively coupled with an independent preprogrammable micropocessing unit in each machine and to a single control line common to all disk drives. The microprocessing unit is preprogrammed to interact with the power sequencing circuit to provide Enable/Disable signals to the control line and to sense the state of the control line. In particular, the microprocessing unit executes a preprogrammed sequence of steps in interaction with the control line to sequence the start-up of each spindle motor irrespective of the number of disk drives coupled to the control line, thereby preventing electrical power overload.

Abstract: Performance monitor apparatus is adapted to monitor various computer program events such as the length of time required to execute a particular program, the number of times a particular program or instruction sequence is executed during some predetermined period, etc. The apparatus includes a buffer for receiving an instruction data word from a data processor and for temporarily storing the data word, a register having a plurality of bistable elements each of which is adapted to produce either a first or second output signal in response to receipt of a first or second operation signal respectively and receipt of a select signal, a select logic circuit for applying a select signal to a particular bistable element identified by certain bits of the instruction data word stored in the buffer, and an operation logic circuit for supplying to the bistable elements either a first or second operation signal as determined by certain other bits of the instruction data word stored in the buffer.

Abstract: A display system using the dispersive Faraday coefficient of a magnetic screen to obtain a color display from white light is disclosed. A beam of energy is directed upon a magnetic screen while concurrently an intensity modulated magnetic field is directed normal to the surface of the magnetic screen. The combination of the heating effect of the energy beam and the magnetic orienting effect of the intensity modulated magnetic field established localized areas of differing magnetic characteristics over the planar surface of the magnetic screen. Subsequently, a polarized beam of white light that floods the magnetic screen is, for each of several wave lengths, differently rotated upon passing through each of the areas of differing magnetic characteristics in the magnetic screen. The beamlets that are formed by the so-differently rotated areas of the polarized white light beam are then passed through an uncrossed analyzer, which beamlets appear as a multicolored projection upon the magnetic screen.

Abstract: A hydraulic control system for the rolling rack of a three table bale wagon wherein the rolling rack is movable along the third table for supporting tiers of bales deposited on the third table by the second table, the control system including a single acting hydraulic cylinder for positively advancing the rolling rack to a first position wherein the third table is ready to receive tiers of bales, apparatus for selectively connecting the hydraulic cylinder with a source of hydraulic fluid under pressure for extending the hydraulic cylinder and thereby moving the rolling rack to the first position, and including a fluid flow line; selective apparatus connected with the fluid flow line for intermittent release of fluid pressure from the fluid flow line so that when mechanical pressure is exerted against the hydraulic cylinder in such a manner as to urge retraction of the cylinder, the retraction may be controlled by intermittent release of pressure from the fluid flow line.

Abstract: In a crop roll forming machine having a reversibly rotatable bale forming means there is provided an improved drive means with tensioning means movably affixed to the frame for cooperative interaction with the drive means and the bale forming means to selectively cause the bale forming means to cease being driven in a first direction and cause it to be driven in an opposing second direction when the tensioning means is moved to a predetermined position so that a completed crop roll is ejected rearwardly from the machine onto the ground.

Abstract: A multi-row crop header for a forage harvester having a plurality of forwardly extending dividers to provide crop passageways therebetween, the inner ends of said dividers being adjustably connected to a transverse frame member to vary the spacings between said passageways, and a rotatable feed assist roller mounted adjacent the inner end of the outermost divider to assist in guidng down crops picked up by said dividers to the inner ends of said passageways for discharge therefrom and prevent hairpinning of said down crops from jamming said header thereby.

Abstract: In a crop roll forming machine having a reversibly rotatable bale forming means and a drive means there is provided a control means affixed to the frame movable between at least a first position and a second position for cooperative interaction with the drive means and the bale forming means to selectively cause the bale forming means to cease being driven in a first direction and cause it to be driven in an opposing second direction when the control means is moved from the first position to the second position so that a completed crop roll is ejected rearwardly from the machine onto the ground.

Abstract: A rotatable cutterhead for a forage harvester having a plurality of parallel support members within plans perpendicular to a central shaft and spaced axially therealong. A plurality of similar chopping blades are affixed in circumferentially spaced relationship to each other around the support members, whereby the interior of said cutterhead is open and susceptible to ingress of cut forage material. Baffle strips extend from each blade inwardly from and adjacent the cutting edge at a sufficient distance and angle to deter the ingress of cut material into the interior of said cutterhead.

Abstract: In a harvesting and threshing machine utilizing at least one cooperative cylinder and rotatable rotor to achieve axial flow threshing and separation of grain bearing crop material there is provided an improved grain collection means underlying the auxiliary separation and discharge means and overlying at least a portion of the primary cleaning and separating means movably mounted to the frame of the machine in such a manner that air flow generated by the cleaning fan is not disturbed by the rotation of the rotor or the beater means of the auxiliary separation and discharge means.

Abstract: An interface which connects input/output (I/O) controllers to a data channel in a data processing system. A bidirectional priority bus is provided interconnecting the channel with the controllers. Each controller is assigned a priority level. When a controller requires service, it signals the channel over a common request line and the channel responds with a channel select signal. Each requesting controller gates a binary number corresponding to its priority level onto the common priority bus. Contending controllers resolve priority among themselves by monitoring the priority bus. If a controller detects a higher priority level than its own level on the bus it removes its priority number from the bus. The highest priority controller then activates an acknowledge signal and places its device address on a bidirectional data bus in response to a ready signal from the channel.