Patents Assigned to The Raytheon Company
  • Patent number: 9348021
    Abstract: Methods and apparatus for performing adaptive motion compensation to remove translational movement between a sensor and a target using data from the sensor. After whitening, data can be processed to select a target and focus frequency components. Dynamic sliding window processing can be performed on processed time domain data to estimate an instantaneous range rate for the target.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: May 24, 2016
    Assignee: Raytheon Company
    Inventor: Aaron C. Wallace
  • Patent number: 9348126
    Abstract: An all-reflective afocal optical system including an aspheric beam steering mirror positioned at an exit pupil of the afocal optical system. In one example, an all-reflective afocal optical imaging system includes a sensor, a afocal optical apparatus including a plurality of mirrors optically coupled together and configured to receive light rays through an entrance pupil of the afocal optical imaging system and to substantially collimate the light rays to provide a collimated optical beam to an exit pupil, and an aspheric beam steering mirror positioned at the exit pupil and configured to receive the collimated optical beam and to direct the collimated optical beam to the sensor.
    Type: Grant
    Filed: November 8, 2011
    Date of Patent: May 24, 2016
    Assignee: RAYTHEON COMPANY
    Inventor: Lacy G. Cook
  • Patent number: 9350366
    Abstract: A loop filter for a phase locked loop (PLL) having fast tuning capability while limiting phase noise. The filter includes a fine tune input port to receive a fine tune signal from the phase detector and a coarse tune input port to receive a coarse tune signal from the coarse tuner. The external coarse tuner provides the majority of the voltage slew on the loop filter while a fine tune control, thus reducing tune time. In one embodiment, the loop filter includes a voltage divider to limit the effective tuning sensitivity and thus control noise induced on a voltage-controlled oscillator from the loop filter. An elliptical filter may be employed to attenuate fractional spurs within the filter output signal.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: May 24, 2016
    Assignee: Raytheon Company
    Inventors: Robert J. Smith, Steven Hand
  • Patent number: 9350917
    Abstract: A method of misregistration correction in a line scanning imaging system includes: generating a model of scan motion over a focal plane of the imaging system, using a coupled system of scan equations with constant coefficients; estimating programmed motion positions across a plurality of detector junction overlap regions via a state transition matrix solution to the scan equations; at each detector junction overlap region, measuring actual motion positions via image correlation of overlapping detectors; generating differences between the actual motion positions and the estimated programmed motion positions; estimating updates to the constant coefficients based on the generated differences; generating corrections from the estimated updates to remove unwanted motion; and applying the updates to the constant coefficients.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: May 24, 2016
    Assignee: Raytheon Company
    Inventors: Sarah A LaFarelle, Archie Henry Muse
  • Patent number: 9350504
    Abstract: Using bearer channels for wireless nodes includes initiating communication among the wireless nodes that include a node and one or more neighbor nodes. An adaptive channel operable to communicate messages between the node and the neighbor nodes is established. One or more bearer channels are selected. The one or more neighbor nodes are notified of the one or more selected bearer channels using the adaptive channel. The node and the neighbor nodes communicate over the bearer channels.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 24, 2016
    Assignee: Raytheon Company
    Inventors: Scott Y. Seidel, Michael R. Franceschini
  • Patent number: 9339974
    Abstract: A fused deposition modeling (FDM) extrusion head is configured to receive control signals from a controller. The FDM extrusion head receives a stream of thermofusible material into an input channel; forces the stream of thermofusible material into a liquefier channel using a mechanical driver; heats the stream of thermofusible material within the liquefier channel to a specified temperature above melting point of the thermofusible material; and receives the heated thermofusible material from an outlet of the liquefier channel and expels the heated thermofusible material through an extrusion tip.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: May 17, 2016
    Assignee: Raytheon Company
    Inventor: Geoffrey Chad Spalt
  • Patent number: 9342094
    Abstract: Embodiments of a multi-processor system and method for synchronization and event scheduling of multiple processing elements are generally described herein. In some embodiments, timing marks are provided to the processing elements and a start-timer command is broadcasted to the processing elements after an initial timing mark. The start-timer command instructs the processing elements to initiate an internal time reference after receipt of a next timing mark. Each of the processing elements maintains a copy of the internal time reference which may be used for synchronized event scheduling.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: May 17, 2016
    Assignee: Raytheon Company
    Inventors: Kassie M. Bowman, Andrew C. Marcum, Philip P. Herb
  • Patent number: 9342511
    Abstract: In an exemplary embodiment, a computer-implemented method includes receiving an instruction to select an output set from an input set, where the output set is a top subset or a bottom subset of the input set, where the input set comprises a plurality of members, and where each member of the input set includes a plurality of bits. A first subset of the plurality of bits is selected. A histogram is generated, by a computer processor, based on the values in the first subset of the plurality of bits. A threshold value of the input set is determined, where the threshold value separates the values of the output set from the values of the remainder of the input set, and where the threshold value is based at least in part on the histogram. The output set is then extracted from the input set based on the threshold value.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: May 17, 2016
    Assignee: RAYTHEON COMPANY
    Inventor: Michael T. Bahns
  • Patent number: 9343328
    Abstract: A semiconductor structure having a substrate; an active device formed in an active semiconductor region of the substrate, the active device having a control electrode for controlling a flow of carriers through the active semiconductor region between a pair of electrical contacts; and a photolithographic, thickness non-uniformity, compensation feature, disposed on the surface substrate off of the active semiconductor region. In one embodiment the feature comprises pads on the surface of the substrate and off of the active semiconductor region.
    Type: Grant
    Filed: January 5, 2015
    Date of Patent: May 17, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Paul J. Duval, Paul M. Ryan, Christopher J. MacDonald
  • Patent number: 9343816
    Abstract: An antenna array includes a plurality of radiating elements disposed on a layer that is situated above an egg crate structure that is formed of interconnected dielectric panels. In some embodiments, balun circuitry is disposed on at least some of the dielectric panels of the egg crate structure for use in feeding corresponding radiating elements of the array in a balanced manner. Ground plane blocks may also be coupled to some or all of the dielectric panels to provide circuit shielding and/or to form a ground plane for the array antenna.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: May 17, 2016
    Assignee: Raytheon Company
    Inventors: Jar J. Lee, Stan W. Livingston
  • Patent number: 9335947
    Abstract: Embodiments relate to an inter-processor memory. An aspect includes a plurality of memory banks, each of the plurality of memory banks comprising a respective plurality of parallel memory modules, wherein a number of the plurality of memory banks is equal to a number of read ports of the inter-processor memory, and a number of parallel memory modules within a memory bank is equal to a number of write ports of the inter-processor memory. Another aspect includes each memory bank corresponding to a single respective read port of the inter-processor memory, and wherein, within each memory bank, each memory module of the plurality of parallel memory modules is writable in parallel by a single respective write port of the inter-processor memory.
    Type: Grant
    Filed: June 30, 2014
    Date of Patent: May 10, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Pen C. Chien, Frank N. Cheung, Kuan Y. Huang
  • Patent number: 9335409
    Abstract: A bistatic synthetic aperture radar (SAR) imaging system and method include: combining each radar return pulse from airborne radar platforms with a sinusoid; deskewing each reduced radar return pulse; estimating motion parameters based on a maximum likelihood estimation (MLE); performing MLE motion correction to generate motion-corrected radar return pulses; acquiring position and velocity estimates of the airborne radar platforms and scattering locations; defining bistatic range and velocity vectors; defining new bistatic range and velocity vectors in a new set of orthogonal axes; projecting vector distance differences between the radar scattering locations along the new set of orthogonal axes to generate new range and velocity measurements along the new set of orthogonal axes; converting the new range and velocity measurements to map Doppler frequency into cross-range; and forming a bistatic SAR image in range and cross-range based on cross-range extent derived from the Doppler frequency mapping.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: May 10, 2016
    Assignee: Raytheon Company
    Inventors: Theagenis J. Abatzoglou, Johan E. Gonzalez
  • Patent number: 9335218
    Abstract: A digital bolometer architecture provides dynamic control of a simultaneous integration time for all pixels, with a temporal response that is more uniform than conventional bolometers and lacks frame cross-talk from decay tails, and which supports sub-frame measurement for on readout computational imaging. This is accomplished by replacing resistive pixel temperature sensing with continuous optical interferometric measurement and subsequent signal accumulation. Balanced reference sensors allow rejection of temperature differences across the thermal sink. The thermal time constant of the pixels is substantially reduced and the lost SNR is recovered by integration of the measured signals, using a programmable integration time.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 10, 2016
    Assignee: Raytheon Company
    Inventor: Darin S. Williams
  • Patent number: 9335414
    Abstract: In one aspect, a frequency agile LADAR (laser detection and ranging) sensor includes a transmitter configured to provide laser pulses towards a target, a receiver configured to receive a reflected signal from the target and control circuitry configured to tune an optical frequency of a first laser pulse of the laser pulses to be different from an optical frequency of a second laser pulse of the laser pulses and tune an optical frequency of the receiver to be different than an optical frequency of a laser pulse most recently transmitted by the transmitter.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: May 10, 2016
    Assignee: Raytheon Company
    Inventor: Victor Leyva
  • Patent number: 9334675
    Abstract: A system includes a structure having a first structural element and a second structural element. The system also includes a latch configured to releasably secure the first structural element to the second structural element. The latch includes first and second portions. The latch also includes a ball lock configured to hold the first and second portions of the latch together when the ball lock is engaged. The ball lock is also configured to allow the first and second portions of the latch to separate when the ball lock is disengaged. The latch further includes a shape memory material member configured to fracture when exposed to an elevated temperature and thereby disengage the ball lock. The shape memory material member could include an elongated structure that is configured to decrease in length when exposed to the elevated temperature. The elongated structure could have at least one notch.
    Type: Grant
    Filed: August 15, 2012
    Date of Patent: May 10, 2016
    Assignee: Raytheon Company
    Inventors: Frederick B. Koehler, Ward D. Lyman
  • Patent number: 9335126
    Abstract: An offset aperture gimbaled optical system comprises a gimbal and an optics assembly that is mounted on an inner gimbal and offset radially from an axis of symmetry (and rotation axis) of a conformal dome. An optical corrector adjacent the inner surface of the conformal dome encompasses the field-of-view of the optics assembly as the inner gimbal rotates about its rotation axis. The corrector is fixed with respect to the inner gimbal's rotation axis while it rotates about the axis of symmetry. The optical corrector comprises an aspheric transparent arch having an optical corrector shape and position responsive to a shape of the conformal dome at the offset position of the optics assembly. In different applications, the offset aperture provides for reduced optical aberrations and improved utilization of the available packaging volume to accommodate multiple offset aperture optics assemblies.
    Type: Grant
    Filed: July 17, 2013
    Date of Patent: May 10, 2016
    Assignee: Raytheon Company
    Inventors: Chadwick B. Martin, David J. Knapp, Gregory P. Hanauska
  • Patent number: 9334154
    Abstract: A sealed package having a device disposed on a wafer structure and a lid structure boned to the device wafer. The device wafer includes: a substrate; a metal ring disposed on a surface portion of substrate around the device and a bonding material disposed on the metal ring. The metal ring extends laterally beyond at least one of an inner and outer edge of the bonding material. A first layer of the metal ring includes a stress relief buffer layer having a higher ductility than that of the surface portion of the substrate and a width greater than the width of the bonding material. The metal ring extends laterally beyond at least one of the inner and outer edges of the bonding material. The stress relief buffer layer has a coefficient of thermal expansion greater than the coefficient of expansion of the surface portion of the substrate and less than the coefficient of expansion of the bonding material.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: May 10, 2016
    Assignee: RAYTHEON COMPANY
    Inventors: Adam M. Kennedy, Buu Q. Diep, Stephen H. Black, Tse E. Wong, Thomas Allan Kocian, Gregory D. Tracy
  • Publication number: 20160126920
    Abstract: A matching network requiring a predetermined shunt capacitance in a transformation of the impedance at the output to a transistor to a load. The matching network includes a vertically stacked shunt capacitor, for providing the entire predetermined capacitance, and a series DC blocking capacitor.
    Type: Application
    Filed: October 31, 2014
    Publication date: May 5, 2016
    Applicant: Raytheon Company
    Inventor: Valery S. Kaper
  • Patent number: 9330882
    Abstract: A particle beam detector is disclosed. The particle beam detector can include a particle beam receiving portion configured to convert particle beam energy to heat, and a plurality of temperature measuring devices disposed about the particle beam receiving portion. A location of a particle beam on the particle beam receiving portion can be determined by a temperature difference between at least two of the plurality of temperature measuring devices.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: May 3, 2016
    Assignee: Raytheon Company
    Inventors: Bruce Chignola, Timothy M. Norcott, Brandon W. Blackburn, Paul F. Martin, Kenneth A. Levenson
  • Patent number: 9331153
    Abstract: A structure is provided having: (A) a first silicon layer and a first silicon dioxide layer over the first silicon layer; and (B) a second silicon layer and a second silicon dioxide layer over the second silicon layer; the first silicon dioxide layer bonded to the second silicon dioxide layer. An upper surface of the first silicon layer is polished to reduce its thickness. A III-V layer is grown on the upper surface of the thinned silicon layer. A III-V device is formed in the III-V layer together with a strip conductor connected to the formed. The second silicon layer, the second silicon dioxide layer and the first silicon dioxide layer are successively removed to expose a bottom surface of the first silicon layer. A ground plane conductor is formed on the exposed bottom surface, the strip conductor and the ground plane conductor providing a microstrip transmission line.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: May 3, 2016
    Assignee: RAYTHEON COMPANY
    Inventor: Jeffrey R. LaRoche