Abstract: Various semiconductor wafers and their methods of fabrication are disclosed. One exemplary process comprises, forming a layer consisting essentially of aluminum nitride on a first wafer. The first wafer includes a substrate. The process also comprises bonding a second wafer to the first wafer. The aluminum nitride layer is interposed between the substrate and the second wafer after the bonding step. The process also comprises separating the first and second wafers to form a semiconductor on insulator (SOI) wafer. The SOI receives a layer of semiconductor material from the second wafer during the separating step. The SOI wafer includes the layer of semiconductor material, the layer consisting essentially of aluminum nitride, and the substrate after the separating step.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist of a donor or acceptor material.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies.

Abstract: An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.

Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.

Abstract: A superlattice and method for forming that superlattice are disclosed. In particular, an engineered layered single crystal structure forming a superlattice is disclosed. The superlattice provides p-type or n-type conductivity, and comprises alternating host layers and impurity layers, wherein: the host layers consist essentially of a semiconductor material; and the impurity layers consist essentially of a corresponding donor or acceptor material.

Abstract: A method of forming contacts to an n-type layer and a p-type layer of a semiconductor device includes depositing a dielectric layer on the n-type layer and the p-type layer. A pattern is formed in the dielectric layer, the pattern having a plurality of metal contact patterns for the semiconductor device. A first metal layer is deposited into the plurality of metal contact patterns, and a second metal layer is deposited directly on the first metal layer. External contacts for the semiconductor device are formed, where the external contacts include the second metal layer.

Abstract: An electronic circuit structure is formed with first and second dies bonded together. A first active layer is formed in the first die, and a second active layer is formed in the second die. The first and second dies are bonded together, with an isolation capacitor, through which the first and second active layers communicate, disposed between the first and second dies.

Abstract: Light emitting semiconductor junctions are disclosed. An exemplary light emitting junction has a first electrical contact coupled to a first side of the junction. The exemplary junction also has a second electrical contact coupled to a second side of the junction. The exemplary junction also has a region of set straining material that exerts a strain on the junction and alters both: (i) an optical polarization, and (ii) an emission wavelength of the junction. The region of set straining material is not on a current path between said first electrical contact and said second electrical contact. The region of set straining material covers a third side and a fourth side of the light emitting junction along a cross section of the light emitting junction. The light emitting semiconductor junction device comprises a three-five alloy.

Abstract: A method of forming contacts to an n-type layer and a p-type layer of a semiconductor device includes depositing a dielectric layer on the n-type layer and the p-type layer. A pattern is formed in the dielectric layer, the pattern having a plurality of metal contact patterns for the semiconductor device. A first metal layer is deposited into the plurality of metal contact patterns, and a second metal layer is deposited directly on the first metal layer. External contacts for the semiconductor device are formed, where the external contacts include the second metal layer.

Abstract: Light emitting semiconductor junctions are disclosed. An exemplary light emitting junction has a first electrical contact coupled to a first side of the junction. The exemplary junction also has a second electrical contact coupled to a second side of the junction. The exemplary junction also has a region of set straining material that exerts a strain on the junction and alters both: (i) an optical polarization, and (ii) an emission wavelength of the junction. The region of set straining material is not on a current path between said first electrical contact and said second electrical contact. The region of set straining material covers a third side and a fourth side of the light emitting junction along a cross section of the light emitting junction. The light emitting semiconductor junction device comprises a three-five alloy.

Abstract: An integrated circuit, including at least two integrated circuit portions mutually spaced on a single electrically insulating die and at least one coupling region on the die to provide capacitive coupling between the otherwise mutually isolated integrated circuit portions, the integrated circuit portions being formed by a plurality of layers on the single die, the layers including metal and dielectric layers and at least one semiconductor layer; wherein at least one of the dielectric layers extends from the integrated circuit portions across the coupling region and at least a corresponding one of the metal layers and/or at least one semiconductor layer extends from each of the integrated circuit portions and partially across the coupling region to form capacitors therein and thereby provide the capacitive coupling between the integrated circuit portions.

Abstract: An isolator assembly is disclosed. The assembly comprises a laminate consisting essentially of a block of homogenous material and a set of electrical contacts. A first die is coupled to a surface of the laminate. An isolation barrier is located entirely above the surface of the laminate. A second die is coupled to the laminate. The second die is galvanically isolated from the first die by the isolation barrier. The second die is in operative communication with the first die via the isolation barrier and a conductive trace on the laminate. The first die, the second die, the laminate, and the isolation barrier are all contained within an assembly package.

Abstract: A method of producing a silicon-on-insulator article, the method including: forming a first aluminum nitride layer thermally coupled to a first silicon substrate; forming a second aluminum nitride layer thermally coupled to a second substrate, the second substrate including at least a surface layer of silicon; bonding the first and second aluminum nitride layers of the first and second substrates together so that the first and second aluminum nitride layers are disposed between the first and second substrates; and removing most of the second substrate to leave a layer of silicon that is electrically insulated from but thermally coupled to the first silicon substrate by the first and second aluminum nitride layers.

Abstract: An integrated circuit, including: at least three integrated circuit portions mutually spaced on a single electrically insulating die, the integrated circuit portions being mutually galvanically isolated; and signal coupling structures on the die to allow communication of signals between the integrated circuit portions while maintaining the galvanic isolation therebetween.

Abstract: An optoelectronic device, including a semiconductor body having a surface to receive photons and a plurality of doped regions of opposite doping polarities, the doped regions extending substantially from the surface of the semiconductor body and into the semiconductor body, and being arranged in one or more pairs of opposite doping polarities such that each pair of doped regions forms a corresponding space charge region having a corresponding electric field therein, the space charge region extending substantially from the surface of the semiconductor body and into the semiconductor body such that photons entering the semiconductor body through the surface and travelling along paths within the space charge region generate electron-hole pairs in the space charge region that are separated in opposing directions substantially orthogonal to the photon paths by the electric field and collected by the corresponding pair of doped regions, thereby providing an electrical current to be conducted from the device.

Abstract: A USB isolator integrated circuit, including: an isolation barrier disposed between an upstream portion and a downstream portion of the integrated circuit to provide galvanic isolation therebetween; a first USB 2.0 interface configured to receive and transmit USB 2.0 compliant signals between the upstream portion of the integrated circuit and an upstream USB entity; a second USB 2.0 interface configured to receive and transmit USB 2.0 compliant signals between the downstream portion of the integrated circuit and a downstream USB entity; a plurality of signal coupling components configured to allow communication between the upstream portion and the downstream portion of the integrated circuit to allow the upstream USB entity and the downstream USB entity to communicate therebetween using a USB 2.0 protocol while maintaining the galvanic isolation therebetween; and the upstream and downstream portions of the integrated circuit including respective modules configured to automatically detect a USB 2.