Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Abstract: In one aspect, an oxygenated hierarchically porous carbon (an “O-HPC”) is provided, the O-HPC comprising: a hierarchically porous carbon (an “UPC”), the HPC comprising a surface, the surface comprising: (A) first order pores having an average diameter of between about 1 ?m and about 10 ?m; and (B) walls separating the first order pores, the walls comprising: (1) second order pores having a peak diameter between about 7 nm and about 130 nm; and (2) third order pores having an average diameter of less than about 4 nm, wherein at least a portion of the HPC surface has been subjected to O2 plasma to oxygenate and induce a negative charge to the surface. In one aspect, the O-HPC further comprises metal nanoparticles dispersed within the first, second, and third order pores. Methods for making and using the metal nanoparticle-impregnated O-HPCs are also provided.

Abstract: In one aspect, an oxygenated hierarchically porous carbon (an “O-HPC”) is provided, the O-HPC comprising: a hierarchically porous carbon (an “HPC”), the HPC comprising a surface, the surface comprising: (A) first order pores having an average diameter of between about 1 ?m and about 10 ?m; and (B) walls separating the first order pores, the walls comprising: (1) second order pores having a peak diameter between about 7 nm and about 130 nm; and (2) third order pores having an average diameter of less than about 4 nm, wherein at least a portion of the HPC surface has been subjected to O2 plasma to oxygenate and induce a negative charge to the surface. In one aspect, the O-HPC further comprises metal nanoparticles dispersed within the first, second, and third order pores. Methods for making and using the metal nanoparticle-impregnated O-HPCs are also provided.

Abstract: Methods of making molybdenum sulfide (MoS2) on a stretchable substrate are disclosed. The method includes magnetron sputtering MoS2 onto a stretchable substrate, such as a stretchable polymeric material, at low temperatures to form a film precursor, and illumination annealing the film precursor to form high quality MoS2. The illumination source may be a laser or other source of radiation. Also, two-dimensional nanoelectronic devices made by the methods and/or from the high quality MoS2 are disclosed.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.

Abstract: In one aspect, an oxygenated hierarchically porous carbon (an “O-HPC”) is provided, the O-HPC comprising: a hierarchically porous carbon (an “HPC”), the HPC comprising a surface, the surface comprising: (A) first order pores having an average diameter of between about 1 ?m and about 10 ?m; and (B) walls separating the first order pores, the walls comprising: (1) second order pores having a peak diameter between about 7 nm and about 130 nm; and (2) third order pores having an average diameter of less than about 4 nm, wherein at least a portion of the HPC surface has been subjected to O2 plasma to oxygenate and induce a negative charge to the surface. In one aspect, the O-HPC further comprises metal nanoparticles dispersed within the first, second, and third order pores. Methods for making and using the metal nanoparticle-impregnated O-HPCs are also provided.

Abstract: A method for processing image or video data is performed in an image processing pipeline. Color filtered mosaiced raw image or video data is received. A one-level wavelet transform of subbands of the color filtered mosaiced raw image or video data to provide LL, HH, LH and HL subbands. The LH and HL subbands are de-correlated by summing and difference operations to provide decorrelated sum and difference subbands. Additional n-level wavelet transformation on the sum and difference subbands and the LL and HH subbands to provide sparsified subbands for encoding. LL and HH and sum subbands are recombined into standard color images e.g., red, green, and blue color components, which are subsequently processed by color correction, white balance, and gamma correction. The sparsified subbands are encoded.

Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Abstract: A system is provided for interfacing a Full Authority Digital Engine Control (FADEC) system with engine sensors and actuators using miniaturized Low Temperature Co-fired Ceramic (LTCC) substrates operating as smart notes that communicate digitally over a data bus to a miniaturized LTCC operating as a data concentrator. The use of smart nodes and/or data concentrators assembled on LTCC substrates provides enhanced thermal and vibration performance along with resistance to hydration, improved reliability and reduced overall size of the circuitry unit.

Abstract: Methods of making molybdenum sulfide (MoS2) on a stretchable substrate are disclosed. The method includes magnetron sputtering MoS2 onto a stretchable substrate, such as a stretchable polymeric material, at low temperatures to form a film precursor, and illumination annealing the film precursor to form high quality MoS2. The illumination source may be a laser or other source of radiation. Also, two-dimensional nanoelectronic devices made by the methods and/or from the high quality MoS2 are disclosed.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Abstract: A device for controlling an industrial system comprises an input block and a reference value predicter. The reference value predicter includes a disturbance predicter, a state predicter, and a model parameter predicter. A model updater updates the model of the industrial system based on the predicted state and the predicted parameters. A one-prediction-step calculator of the reference value predicter calculates a prediction step based on the predicted disturbances and the model of the system. The device further includes a matrix updater and a linear solver that includes a memory structure such that each row of Jacobian and gradient matrices may be processed in parallel, a pivot search block that determines a maximum element in a column of the Jacobian and gradient matrices, and a pivot row reading block. Moreover, the device further includes a solution updater that updates the solution for an iteration step and controls the iteration process and an output block that sends a solution to the industrial system.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to an input voltage signal as the input voltage signal propagates through the resistive memories generating a first output voltage signal and to provide a resistance to a first error signal that propagates through the resistive memories generating a second output voltage signal. A comparator generates the first error signal that is representative of a difference between the first output voltage signal and the desired output signal and generates the first error signal so that the first error signal propagates back through the plurality of resistive memories. A resistance adjuster adjusts a resistance value associated with each resistive memory based on the first error signal and the second output voltage signal to decrease the difference between the first output voltage signal and the desired output signal.

Abstract: An analog neuromorphic circuit is disclosed having resistive memories that provide a resistance to each corresponding input voltage signal. Input voltages are applied to the analog neuromorphic circuit. Each input voltage represents a vector value that is a non-binary value included in a vector that is incorporated into a dot-product operation with weighted matrix values included in a weighted matrix. A controller pairs each resistive memory with another resistive memory. The controller converts each pair of resistance values to a single non-binary value. Each single non-binary value is mapped to a weighted matrix value included in the weighted matrix that is incorporated into the dot-product operation with the vector values included in the vector. The controller generates dot-product operation values from the dot-product operation with the vector and the weighted matrix where each dot-product operation is a non-binary value.

Abstract: Systems and methods for finding the solution to a system of linear equations include use of a reconfigurable hardware based real-time computational solver. The solver apparatus solves systems of linear equations by applying Gauss-Jordan Elimination to an augmented matrix in parallel on reconfigurable hardware consisting of parallel data processing modules, reusable memory blocks and flexible control logic units, which can greatly accelerate the solution procedure.

Abstract: Lithium sulfur batteries are described, especially ones that are flexible for wearing about an appendage of a wearer. Such batteries have a lithium metal anode, a sulfur cathode comprising sulfur, a conductive carbon, a lithium supertonic solid-state conductor, and a dendritic or hyperbranched polymer binder, an electrolyte layer between the lithium metal anode and the sulfur cathode, and a current collector positioned on the sulfur cathode opposite the electrolyte layer.

Abstract: An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.

Abstract: A crossbar circuit determines a match of N bits of data to at least one of M target words simultaneously. The circuit comprises N inputs (one per data bit) and M outputs (one per target word). For each of the M target words, the circuit comprises N?1 biased bits, where each biased bit includes a first data memristor coupled to a corresponding one of the N inputs; a second data memristor coupled to the corresponding one of the N inputs, where the corresponding one of the N inputs is inverted before reaching the second data memristor; and two biasing memristors. Further, the circuit comprises a general bit comprising a first data memristor coupled to the input that does not correspond to any of the biased bits; and a second data memristor coupled to the input that does not correspond to any of the biased bits and is inverted.