Abstract: A system for checking and controlling a sequence of operations including a plurality of logic circuits corresponding to the number of operations. A bistable latch circuit has complementary outputs connected to inputs of two gates. A counter counts timing pulses and has its output connected to another input of each gate. If a signal is received by the latch indicating completion of an operation prior to the counter reaching a predetermined count, one gate provides a signal enabling the sequence of operations to continue. If the counter reaches the predetermined count prior to receipt of the signal by the latch, the other gate provides a signal to interrupt the sequence of operations.