Abstract: A NULL convention-threshold gate receives a plurality of inputs, each having an asserted state and a NULL state. The threshold gate switches its output to an asserted state when the number of asserted inputs exceeds a threshold number. The threshold gate switches its output to the NULL state only after all inputs have returned to NULL. Signal states may be implemented as distinct current levels.

Abstract: A method for designing a multi-rail asynchronous circuit is provided. The method includes providing a circuit having n circuit paths, defining a plurality of nodes, each node having an n-rail signal output and at least one n-rail signal input, each rail of the n-rail signal input being connected to a different one of the plurality of circuit paths, and adding completeness detection to each of the plurality of nodes, completion detection for a downstream one of the plurality of nodes being at least partially based on completion detection from an upstream one of the plurality of nodes. Signals propagate along the plurality of data paths independent of the completeness detection.

Abstract: A switching element and method for asynchronous logic switches an output signal according to a switching-logic relationship between or among input signals. Input signals may assume at least a DATA value, a NULL value, and an INTERMEDIATE value. Input signals may also assume multiple DATA values. The element and method generates an output which assumes a NULL value when all input signals are NULL, and assumes DATA and INTERMEDIATE values in accordance with transform rules. Output signals may also assume an INTERMEDIATE value. DATA, NULL and INTERMEDIATE values may be encoded on to a number of signal lines. Transform rules may be threshold switching rules, where the output switches to a DATA output when a number of DATA inputs is greater than a threshold.

Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Abstract: An asynchronous FIFO using Asynchronous NULL Convention LOGIC (NCL) to facilitate interfacing between multiple non-synchronous systems with a minimum of design and verification. Multiple interfaces, configurations, means for minimizing latency, and capabilities for datastream processing are also incorporated.

Abstract: An m-of-n threshold gate is disclosed having an output stated derived from the voltage of a signal node. A “Go-to-Data” circuit pulls the signal node to a first state, corresponding to an ASSERTED (logically meaningful) output when a threshold number of inputs is in the ASSERTED state. A “Go-to-NULL” circuit pulls the signal node to a second state, corresponding to a NULL (logically meaningless) output when all inputs are in the NULL state. In a semi-dynamic embodiment, a weak feedback transistor holds the signal node in a predetermined state when some, but less than the threshold number of inputs is ASSERTED. In a dynamic embodiment, the signal node becomes isolated when less than the threshold number of inputs is ASSERTED, but holds sufficient charge to maintain the signal node in a state that existed at the time of isolation. A variety of GTN circuits are disclosed.

Abstract: An asynchronous FIFO using Asynchronous NULL Convention LOGIC (NCL) to facilitate interfacing between multiple non-synchronous systems with a minimum of design and verification. Multiple interfaces, configurations, means for minimizing latency, and capabilities for datastream processing are also incorporated.

Abstract: A NULL convention asynchronous register regulates wavefronts of signals through a NULL convention sequential circuit. The asynchronous register receives a control signal from a downstream circuit when the downstream circuit is ready to receive a new wavefront. Wavefronts alternate between meaningful data and NULL. The asynchronous register further generates a feedback signal to upstream circuits so that upstream circuits generate a wavefront when the sequential circuit is ready to receive the wavefront. Asynchronous registers can be used to create a variety of architectures, and to store data, as in a sequential circuit (state machine).

Abstract: Threshold logic gates are disclosed that respond to signals that may assume at least a first state having an arithmetic or logic meaning, and a second NULL state that has no arithmetic or logic meaning. Threshold values may be equal to or less than the number of input signal lines. Threshold gates switch their outputs from NULL to a meaningful state when the threshold number of inputs assume meaningful states. Gates will hold outputs in a meaningful (or non-null) state when the number of asserted inputs remains positive, even if the number is less than the threshold. In one embodiment, threshold gates include a "FLASH" input that forces the gate to NULL. In another embodiment, threshold gates include one or more "SET" inputs that drive the gate output to NULL or to a meaningfull state.

Abstract: An asynchronous register with embedded acknowledge collection is disclosed. The asynchronous register includes a data threshold circuit for generating data or NULL values at an output signal line based upon an evaluation of at least one data input value and an acknowledgment collection circuit, embedded in the data threshold circuit, for collecting a plurality of acknowledge signals and resolving the acknowledge signals for controlling, in combination with the at least one data input value, the passing of the data or NULL values to the output signal line. The acknowledgment collection circuit includes an M of N acknowledge collection circuit, wherein N is an integer representing the number of acknowledge signals being resolved and M representing a threshold, wherein M.ltoreq.N.

Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume a DATA state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of DATA inputs exceeds the threshold value. The gate preferably exhibit hysteresis such that the output remains DATA while the number of DATA inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, and array of simplified threshold elements is used to form more complex threshold gates.

Abstract: A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which includes a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume an ASSERTED state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of ASSERTED inputs exceeds the threshold value. In the preferred embodiment, the gate exhibits hysteresis such that the output remains ASSERTED while the number of ASSERTED inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, an array of simplified threshold elements is used to form more complex threshold gates.

Abstract: A threshold gate with registration embedded in the threshold logic is disclosed. A go-to-NULL network and a go to-data network receives data input having an asserted state and a NULL state. A directive or acknowledge signal is received by the embedded registrations network. The directive signal indicates whether an asserted state or the NULL state is desired at the output signal line. A data processing network is coupled to the go-to-NULL network to provide an output signal based upon the go-to-NULL network, the go-to-data network and the registration network. The go-to-data network provides a network of switches that cause an asserted state at the output signal line when a number of the data inputs in the asserted state exceeds a predetermined threshold and the acknowledge signal is in the asserted state. The go-to-NULL network provides a network of switches that cause a NULL state at the output signal line when all of the data inputs are in the NULL state and the acknowledge signal is in the NULL state.

Abstract: An electronic data processing circuit is disclosed having at least an instruction memory, an instruction decoder; and a slot structure. The slot structure is characterized by a plurality of slots. Each slot has at least: (1) an address register (2) a data register, (4) a function register, and (3) a monitoring circuit. Each slot asynchronously performs operations defined by the information content of their respective address register, data register and function register when complete information is present.

Abstract: A NULL convention logic bus includes: a plurality of bus transmission lines; a plurality of NULL convention transmitter ports; and a plurality of NULL convention receiver ports. Each NULL convention transmitter port propagates alternating wavefronts of data an NULL across the bus transmission lines to a NULL convention receiver port. A pipeline bus includes NULL convention storage registers at the transmitter ports. A FIFO pipeline bus includes NULL convention storage registers at the receiver ports. A NULL convention register file includes: a NULL convention input register; and a plurality of NULL convention storage registers. The input register synchronously propagates alternating wavefronts of NULL and data to an addressed NULL convention storage register.

Abstract: A NULL convention logic element comprises an input, an output and a threshold switching circuit. The input receives NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The output produces output NULL convention signals that are encoded onto a plurality of physical input signal lines that can assume at least a first meaningful signal state indicating data, a NULL signal state which has no logic meaning and third signal state distinct from the first and second signal states. The threshold switching circuit triggers changes of the output signal state to NULL in response to the states of all the input signals becoming NULL.

Abstract: An interface circuit between NULL Convention Logic and non-NULL convention memory includes: a first conversion circuit which converts NULL convention address signals to non-NULL address signals. A non-NULL convention memory circuit, e.g., a conventional binary memory, generates non-NULL data signals in response to the non-NULL address signals. A second conversion circuit converts the non-NULL data signals to NULL convention data signals. A timing circuit controls DATA and NULL wavefronts to and through the non-NULL memory.