Abstract: A structure of a substrate for a high-density semiconductor package is provided. The structure of the substrate comprises a metal substrate and an interconnect substrate disposed on the second surface of the metal substrate. The interconnect substrate comprises at least one or more metal and inter-metal dielectric layers comprising a plurality of traces/lines, pads and vias appropriate for the design. One or more dice are attached to the top surface of the metal substrate, wire bonds are used to connect the dice through open slots on the metal substrate to the Ni/Au plated pads on the interconnect substrate. The uppermost wiring layers are electrically connected to the ball pads on the bottom surface through a plurality of wiring layers and conductive vias. The ball pads are attached to the lowest wiring layer.

Abstract: A new method is provided for mounting high-density IC semiconductor devices. A layer of epoxy is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the epoxy layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of epoxy are created where the layer of epoxy is exposed. One or more IC semiconductor die are inserted into the cavities, are electrically connected to the openings that have been created in the layer of epoxy. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.

Abstract: The process of the invention starts with a metal panel, overlying the metal panel is created an interconnect substrate making use of BUM and thin film processing technology while the process of the invention enables the use of stacked vias and merged vias for the connection of the flip chip bumps. The process of the invention creates, for instance, two patterned layers on the surface of the metal panel whereby the metal panel is used as the ground terminal of the power supply. The first layer that is created on the surface of the metal panel can be the power supply layer (this layer can also be used for some fan-out interconnect lines), the second layer that is created on the surface of the metal panel is primarily used for (fan-out) interconnect lines. The flip chip bumps are, under the process of the invention, connected to the second layer of the interconnect substrate.

Abstract: A method is provided for mounting high-density wire bond semiconductor devices. A layer of dielectric is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the dielectric layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed. One or more wire bond semiconductor die are inserted into the cavities, are die bonded and wire bonded to the openings that have been created in the layer of dielectric. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.

Abstract: A new method is provided for mounting high-density flip chip BGA devices. A dielectric layer is first deposited over the first surface of a metal panel. One or more thin film interconnect layers are created on top of the dielectric layer. The interconnect layers are patterned in succession to create metal interconnect pattern. The BUM technology allows for the creation of a succession of layers over the thin film layers. The BUM layers can be used for power or ground distribution and for signal or fan-out interconnect. A cavity is etched on the second surface of the metal panel. A laser is used to create openings for flip chip pad contacts. The panel is subdivided into individual substrates. The method of the invention can also be applied to Land Grid Array and Pin Grid Array devices.

Abstract: A new method is provided for mounting high-density wire bond semiconductor devices. A layer of dielectric is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the dielectric layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed. One or more wire bond semiconductor die are inserted into the cavities, are die bonded and wire bonded to the openings that have been created in the layer of dielectric. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.

Abstract: A new method is provided for packaging high-density IC semiconductor devices. A metal substrate is provided, a layer of dielectric is deposited over the first surface of the metal panel. One or more interconnect layers are then created on top of the dielectric layer, the interconnect layers, which can be thin film interconnect layers, are patterned using maskless exposure equipment. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed in the openings in the metal substrate thereby providing points of electrical contact to the second surface of the interconnect substrate. Holes are created in the first surface of the interconnect substrate thereby providing points of electrical contact to the first surface of the interconnect substrate. Bare semiconductor devices and/or packaged semiconductor devices can be attached on one or both sides of the interconnect substrate.

Abstract: A new method is provided for high-density thin film interconnect processing. A thin layer of epoxy is deposited over a substrate surface, a via pattern is created in the epoxy layer, the surface of the epoxy is subjected to a process of swell and etch. A metal plating base is formed on the surface of the dielectric using electroless seeding for the metal deposition. A layer of photoresist is deposited over the plating base and is patterned and etched to create the pattern of the interconnect lines. Semi-additive plating of the interconnect pattern is performed to the plating base. The photoresist is removed. The plating base is removed from between the pattern of the interconnect lines using micro etching thereby creating the interconnect lines. A layer of dielectric is deposited over the surface of the created layer of interconnect lines. A via pattern is created in the dielectric layer. The process may be repeated more than once. Electrical contacts are made to the top metal pads through the top vias.

Abstract: A new method is provided for the testing of complex, high density flip chip packages. A temporary electrical short is provided by a layer of metal for all the interconnect metal lines of the package, vias are created in a surface of the package for the connection of the flip chips to the package. These vias are plated using either copper or copper followed by nickel and gold. The process of plating requires uninterrupted electrical paths between the vias that are being plated and the layer of metal that provides a temporary electrical short. Where this uninterrupted electrical paths is not present, due to problems of poor via creation or problems of opens in the interconnect lines of the package, the vias will be improperly plated and can as a result be readily identified. The metal layer that has provided the common short between all interconnect lines of the package is now patterned and probed for problems of shorts or opens.

Abstract: A new method is provided for mounting high-density IC semiconductor devices. A layer of epoxy is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the epoxy layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of epoxy are created where the layer of epoxy is exposed. One or more IC semiconductor die are inserted into the cavities, are electrically connected to the openings that have been created in the layer of epoxy. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.

Abstract: A new method is provided for mounting high-density IC semiconductor devices. A layer of epoxy is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the epoxy layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of epoxy are created where the layer of epoxy is exposed. One or more IC semiconductor die are inserted into the cavities, are electrically connected to the openings that have been created in the layer of epoxy. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.

Abstract: A new method is provided for mounting high-density wire bond semiconductor devices. A layer of dielectric is deposited over the first surface of a metal panel. One or more thin film interconnect layers are then created on top of the dielectric layer. The BUM technology allows for the creation of a succession of layers over the thin film layers. The combined layers of thin film and BUM form the interconnect substrate. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed. One or more wire bond semiconductor die are inserted into the cavities, are die bonded and wire bonded to the openings that have been created in the layer of dielectric. Openings are created in the bottom BUM layer; solder balls are inserted and attached to this BUM layer for the completion of the Ball Grid Array (BGA) package.

Abstract: A new method is provided for creating high-density packages for wire bonded chips. The invention uses a combination of BUM technology and thin film deposition techniques to create the required interface between the contact points of the BGA device and the contact balls of the BGA substrate. Cavities are created on the metal panel substrates for IC chip insertion.

Abstract: A new method is provided for mounting high-density flip chip BGA devices. A dielectric layer is first deposited over the first surface of a metal panel. One or more thin film interconnect layers are created on top of the dielectric layer. The interconnect layers are patterned in succession to create metal interconnect pattern. The BUM technology allows for the creation of a succession of layers over the thin film layers. The BUM layers can be used for power or ground distribution and for signal or fan-out interconnect. A cavity is etched on the second surface of the metal panel. A laser is used to create openings for flip chip pad contacts. The panel is subdivided into individual substrates. The method of the invention can also be applied to Land Grid Array and Pin Grid Array devices.

Abstract: A new method is provided for packaging high-density IC semiconductor devices. A metal substrate is provided, a layer of dielectric is deposited over the first surface of the metal panel. One or more interconnect layers are then created on top of the dielectric layer, the interconnect layers, which can be thin film interconnect layers, are patterned using maskless exposure equipment. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed in the openings in the metal substrate thereby providing points of electrical contact to the second surface of the interconnect substrate. Holes are created in the first surface of the interconnect substrate thereby providing points of electrical contact to the first surface of the interconnect substrate. Bare semiconductor devices and/or packaged semiconductor devices can be attached on one or both sides of the interconnect substrate.