Abstract: An asymmetric multi-core heterogenous parallel processing system includes a first group of graphic processor units (GPUs) and a second group of GPUs. The first and second groups of GPU cores share an instruction set architecture (ISA) such that the first group of GPU cores is capable of executing a portion of the instructions of the ISA, and the second group of GPU cores is capable of executing the entire instruction set of the ISA. An application is capable of utilizing both groups of GPU cores, and is further capable of determining what objects should be rendered on which group of GPU cores.

Abstract: The device and method described in this application relate generally to graphics processing systems utilizing the tile based rendering technique and more specifically relate to the processing of the framebuffer data in graphics processing applications. The present invention discloses techniques to reduce the bandwidth needed to access the color data stored in the framebuffer. A method for adaptive lossy delta based compression of color data is disclosed. The error rate, that is the amount of color data lost during the lossy compression process, is controlled by various parameters of the rendered tiles produced by the graphics processing system. The compression process is driven by a dedicated unit which enables informed compression decisions with controllable error rate so as the output color data can be reliably decompressed to produce the original color data with minimal or no errors.

Abstract: Z-buffer compression may be useful for reducing memory usage bandwidth and for performance optimizations. A trackable method of doing the same may be additionally advantageous, as a lossy z-buffer compression scheme may noticeably alter a displayed object. A z-buffer compression unit receives an uncompressed tile, including a matrix of fragments, each representing a pixel and including a z-value. A minimum and maximum z-values of the tile are determined, and a comparison between each z-value of the tile to the minimum/maximum z-value generates a difference value. Basic tile information is then stored, and a compressed tile is stored in the z-buffer memory if the difference value is below a first threshold, such that each fragment is represented by a difference value and an indicator bit, to indicate if the difference is from the minimum z-value or the maximum z-value. The basic tile information includes the minimum z-value, and the maximum z-value.

Abstract: A multi-core asymmetric graphics processing unit (GPU) includes a first group and second group of GPU cores. The first group of GPU cores has a first microarchitecture and a first power consumption profile. The first group of GPU cores is configured to execute a subset of instructions of an instruction set architecture (ISA). The second group of GPU cores have a second microarchitecture and a second power consumption profile higher than the first power consumption profile, and are configured to execute the entire ISA. The first group and second group of GPU cores may be further differentiated by a number of pipeline stages, number of registers, branching execution, vectorization units, or combinations thereof. A subset of GPU cores in either group may have a different operation frequency. In some embodiments, an executable instruction may include an indicator to ascertain if execution is performed by the first or second group of GPU cores.

Abstract: The device and method described in this application relate generally to graphics processing systems utilizing the tile based rendering technique and more specifically relate to the processing of the framebuffer data in graphics processing applications. The present invention discloses techniques to reduce the bandwidth needed to access the color data stored in the framebuffer. A method for adaptive lossy delta based compression of color data is disclosed. The error rate, that is the amount of color data lost during the lossy compression process, is controlled by various parameters of the rendered tiles produced by the graphics processing system. The compression process is driven by a dedicated unit which enables informed compression decisions with controllable error rate so as the output color data can be reliably decompressed to produce the original color data with minimal or no errors.

Abstract: An exemplary embodiment relates generally to methods and apparatus of operating a computing device to perform approximate memoizations. Computer code analysis methods, special hardware units, and run-time apparatus that allow limited errors to occur are disclosed. A computer code generation process, part of compiler or interpreter of a computing system, targeting to insert special instructions in the software code of a computer program is also disclosed, wherein the special instructions may embed information to manage the approximation of value memoizations. The presented technology may reduce the electric power consumption of a computing system by reusing the results or part of the results of previous arithmetic or memory operations. Run-time hardware apparatus to manage the elimination of the operations and control the error introduced by approximate value memoizations are also disclosed.

Abstract: A set of methods, techniques and hardware is described for compressing image data for memory bandwidth and memory storage reduction in graphics processing systems. The disclosed technology can be used for compressing image data sent to the frame buffer and/or image data residing in the frame buffer. The compression process can be based on an adaptive number of base color points and an adaptive number of quantized color points. An adaptive technique for compressing alpha values based on pre-calculated maps or using an estimated alpha value based on thresholds is also disclosed. An implementation of the disclosed methods has, for example, a low hardware overhead, low buffering requirements, and low and predefined compression latency. Also, the disclosed methods allow, for example, random accesses to compressed image data.

Abstract: An exemplary aspect relates generally to graphics processing systems and more specifically relates to executing vertex and fragment shading operations to a pixel blender device. The technology is at least applicable to graphics processing systems in which vertex and fragment shading operations are executed by dedicated fragment and vertex units or by unified shading units. The graphics processing unit driver is responsible to determine if a shading operation can be assigned to a multi-threaded, multi-format pixel blender. Based on the determination, the fragment shading operations or the vertex shading operations or both are assigned to the pixel blender for execution; the execution of the fragment and/or vertex shading operations by the shader unit(s) is skipped. The determination is based on a code analysis. Forwarding shading operations from the fragment and vertex shaders, i.e.