Patents Assigned to Third Dimension (3D) Semiconductor
  • Patent number: 6635906
    Abstract: A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p(or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under a high reverse bias voltage so as the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.
    Type: Grant
    Filed: October 17, 1997
    Date of Patent: October 21, 2003
    Assignee: Third Dimension (3D) Semiconductor
    Inventor: Xingbi Chen